From: Yicong Yang
Armv8.7 introduces single-copy atomic 64-byte loads and stores
instructions and its variants named under FEAT_{LS64, LS64_V,
LS64_ACCDATA}. These features are identified by ID_AA64ISAR1_EL1.LS64
and the use of such instructions in userspace (EL0) can be trapped.
In order to
From: Yicong Yang
Instructions introduced by FEAT_{LS64, LS64_V, LS64_ACCDATA} is
controlled by HCRX_EL2.{EnALS, EnASR, EnAS0}. Additionally
access of ACCDATA_EL1 for FEAT_LS64_ACCDATA is also affected by
FGT. Configure all of these to allow usage at EL0/1.
This doesn't mean these instruc
From: Yicong Yang
0x35 indicates IMPLEMENTATION DEFINED fault for Unsupported Exclusive or
Atomic access. Add ESR_ELx_FSC definition and corresponding wrapper.
Signed-off-by: Yicong Yang
---
arch/arm64/include/asm/esr.h | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm64
From: Yicong Yang
FEAT_LS64* instructions only support to access Device/Uncacheable
memory, otherwise a data abort for unsupported Exclusive or atomic
access (0x35) is generated per spec. It's implementation defined
whether the target exception level is routed and is possible to
implement
From: Yicong Yang
Armv8.7 introduces single-copy atomic 64-byte loads and stores
instructions and its variants named under FEAT_{LS64, LS64_V,
LS64_ACCDATA}. Add support for Armv8.7 FEAT_{LS64, LS64_V, LS64_ACCDATA}:
- Add identifying and enabling in the cpufeature list
- Expose the support of
From: Yicong Yang
Add tests for FEAT_{LS64, LS64_V, LS64_ACCDATA}. Issue related
instructions if feature presents, no SIGILL should be received.
Since such instructions can only operate on Device memory or
non-cacheable memory, we may received a SIGBUS during the test.
Just ignore it since we
On 2024/12/3 17:38, Marc Zyngier wrote:
> On Mon, 02 Dec 2024 13:55:04 +,
> Yicong Yang wrote:
>>
>> From: Yicong Yang
>>
>> FEAT_LS64* instructions only support to access Device/Uncacheable
>> memory, otherwise a data abort for unsupported Exclusive o
On 2024/12/3 17:38, Marc Zyngier wrote:
> On Mon, 02 Dec 2024 13:55:01 +,
> Yicong Yang wrote:
>>
>> From: Yicong Yang
>>
>> Armv8.7 introduces single-copy atomic 64-byte loads and stores
>> instructions and its variants named under FEAT_{LS64, LS64_V,
From: Yicong Yang
If FEAT_LS64WB not supported, FEAT_LS64* instructions only support
to access Device/Uncacheable memory, otherwise a data abort for
unsupported Exclusive or atomic access (0x35) is generated per spec.
It's implementation defined whether the target exception level is
route
From: Yicong Yang
Using FEAT_{LS64, LS64_V} instructions in a guest is also controlled
by HCRX_EL2.{EnALS, EnASR}. Enable it if guest has related feature.
Signed-off-by: Yicong Yang
---
arch/arm64/include/asm/kvm_emulate.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64
On 2025/4/2 0:15, Oliver Upton wrote:
> On Mon, Mar 31, 2025 at 05:43:19PM +0800, Yicong Yang wrote:
>> From: Yicong Yang
>>
>> 0x35 indicates IMPLEMENTATION DEFINED fault for Unsupported Exclusive or
>> Atomic access. Add ESR_ELx_FSC definition and corresponding w
On 2025/4/3 17:04, Suzuki K Poulose wrote:
> On 31/03/2025 10:43, Yicong Yang wrote:
>> From: Yicong Yang
>>
>> Instructions introduced by FEAT_{LS64, LS64_V} is controlled by
>> HCRX_EL2.{EnALS, EnASR}. Configure all of these to allow usage
>> at EL0/1.
>>
On 2025/4/2 0:13, Oliver Upton wrote:
> Hi Yicong,
>
> On Mon, Mar 31, 2025 at 05:43:20PM +0800, Yicong Yang wrote:
>> From: Yicong Yang
>>
>> If FEAT_LS64WB not supported, FEAT_LS64* instructions only support
>> to access Device/Uncacheable memory, otherwis
On 2025/4/7 13:35, Oliver Upton wrote:
> On Mon, Apr 07, 2025 at 11:33:01AM +0800, Yicong Yang wrote:
>> On 2025/4/2 0:13, Oliver Upton wrote:
>>> On Mon, Mar 31, 2025 at 05:43:20PM +0800, Yicong Yang wrote:
>>>> @@ -1658,6 +1658,25 @@ static int user_m
From: Yicong Yang
Instructions introduced by FEAT_{LS64, LS64_V} is controlled by
HCRX_EL2.{EnALS, EnASR}. Configure all of these to allow usage
at EL0/1.
This doesn't mean these instructions are always available in
EL0/1 if provided. The hypervisor still have the control at
runtime.
S
From: Yicong Yang
Armv8.7 introduces single-copy atomic 64-byte loads and stores
instructions and its variants named under FEAT_{LS64, LS64_V}.
Add support for Armv8.7 FEAT_{LS64, LS64_V}:
- Add identifying and enabling in the cpufeature list
- Expose the support of these features to userspace
From: Yicong Yang
Armv8.7 introduces single-copy atomic 64-byte loads and stores
instructions and its variants named under FEAT_{LS64, LS64_V}.
These features are identified by ID_AA64ISAR1_EL1.LS64 and the
use of such instructions in userspace (EL0) can be trapped. In
order to support the use
From: Yicong Yang
Add tests for FEAT_{LS64, LS64_V}. Issue related instructions
if feature presents, no SIGILL should be received. When such
instructions operate on Device memory or non-cacheable memory,
we may received a SIGBUS during the test (w/o FEAT_LS64WB).
Just ignore it since we only
From: Yicong Yang
0x35 indicates IMPLEMENTATION DEFINED fault for Unsupported Exclusive or
Atomic access. Add ESR_ELx_FSC definition and corresponding wrapper.
Signed-off-by: Yicong Yang
---
arch/arm64/include/asm/esr.h | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm64
From: Marc Zyngier
Add a bit of documentation for KVM_EXIT_ARM_LDST64B so that userspace
knows what to expect.
Signed-off-by: Marc Zyngier
Signed-off-by: Yicong Yang
---
Documentation/virt/kvm/api.rst | 43 --
1 file changed, 36 insertions(+), 7 deletions
From: Yicong Yang
The unsupported exclusive/atomic DABT exception is hand to the
userspace. Provide a way for the userspace to inject this DABT
to the guest if they want to imitate how this is handled on the
host.
Signed-off-by: Yicong Yang
---
arch/arm64/include/asm/kvm_emulate.h | 1
From: Yicong Yang
Instructions introduced by FEAT_{LS64, LS64_V} is controlled by
HCRX_EL2.{EnALS, EnASR}. Configure all of these to allow usage
at EL0/1.
This doesn't mean these instructions are always available in
EL0/1 if provided. The hypervisor still have the control at
runtime.
S
From: Yicong Yang
Armv8.7 introduces single-copy atomic 64-byte loads and stores
instructions and its variants named under FEAT_{LS64, LS64_V}.
These features are identified by ID_AA64ISAR1_EL1.LS64 and the
use of such instructions in userspace (EL0) can be trapped. In
order to support the use
From: Yicong Yang
If FEAT_LS64WB not supported, FEAT_LS64* instructions only support
to access Device/Uncacheable memory, otherwise a data abort for
unsupported Exclusive or atomic access (0x35) is generated per spec.
It's implementation defined whether the target exception level is
route
f-by: Marc Zyngier
Signed-off-by: Yicong Yang
---
arch/arm64/kvm/mmio.c| 27 ++-
include/uapi/linux/kvm.h | 3 ++-
2 files changed, 28 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/kvm/mmio.c b/arch/arm64/kvm/mmio.c
index ab365e839874..04520f2f6010 100644
--- a/
From: Yicong Yang
Armv8.7 introduces single-copy atomic 64-byte loads and stores
instructions and its variants named under FEAT_{LS64, LS64_V}.
Add support for Armv8.7 FEAT_{LS64, LS64_V}:
- Add identifying and enabling in the cpufeature list
- Expose the support of these features to userspace
From: Yicong Yang
Using FEAT_{LS64, LS64_V} instructions in a guest is also controlled
by HCRX_EL2.{EnALS, EnASR}. Enable it if guest has related feature.
Signed-off-by: Yicong Yang
---
arch/arm64/include/asm/kvm_emulate.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64
On 2025/6/26 16:09, Yicong Yang wrote:
> From: Yicong Yang
>
> The unsupported exclusive/atomic DABT exception is hand to the
> userspace. Provide a way for the userspace to inject this DABT
> to the guest if they want to imitate how this is handled on the
> host.
>
Te
From: Yicong Yang
Using FEAT_{LS64, LS64_V} instructions in a guest is also controlled
by HCRX_EL2.{EnALS, EnASR}. Enable it if guest has related feature.
Signed-off-by: Yicong Yang
---
arch/arm64/include/asm/kvm_emulate.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64
From: Yicong Yang
Armv8.7 introduces single-copy atomic 64-byte loads and stores
instructions and its variants named under FEAT_{LS64, LS64_V}.
Add support for Armv8.7 FEAT_{LS64, LS64_V}:
- Add identifying and enabling in the cpufeature list
- Expose the support of these features to userspace
From: Marc Zyngier
Add a bit of documentation for KVM_EXIT_ARM_LDST64B so that userspace
knows what to expect.
Signed-off-by: Marc Zyngier
Signed-off-by: Yicong Yang
---
Documentation/virt/kvm/api.rst | 43 --
1 file changed, 36 insertions(+), 7 deletions
f-by: Marc Zyngier
Signed-off-by: Yicong Yang
---
arch/arm64/kvm/mmio.c| 27 ++-
include/uapi/linux/kvm.h | 3 ++-
2 files changed, 28 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/kvm/mmio.c b/arch/arm64/kvm/mmio.c
index ab365e839874..04520f2f6010 100644
--- a/
From: Yicong Yang
Armv8.7 introduces single-copy atomic 64-byte loads and stores
instructions and its variants named under FEAT_{LS64, LS64_V}.
These features are identified by ID_AA64ISAR1_EL1.LS64 and the
use of such instructions in userspace (EL0) can be trapped. In
order to support the use
From: Yicong Yang
If FEAT_LS64WB not supported, FEAT_LS64* instructions only support
to access Device/Uncacheable memory, otherwise a data abort for
unsupported Exclusive or atomic access (0x35, UAoEF) is generated
per spec. It's implementation defined whether the target exception
lev
From: Yicong Yang
Instructions introduced by FEAT_{LS64, LS64_V} is controlled by
HCRX_EL2.{EnALS, EnASR}. Configure all of these to allow usage
at EL0/1.
This doesn't mean these instructions are always available in
EL0/1 if provided. The hypervisor still have the control at
runtime.
S
From: Yicong Yang
Add tests for FEAT_{LS64, LS64_V}. Issue related instructions
if feature presents, no SIGILL should be received. When such
instructions operate on Device memory or non-cacheable memory,
we may received a SIGBUS during the test (w/o FEAT_LS64WB).
Just ignore it since we only
On 2025/6/27 21:12, Marc Zyngier wrote:
> On Thu, 26 Jun 2025 12:39:41 +0100,
> Yicong Yang wrote:
>>
>> On 2025/6/26 16:51, Marc Zyngier wrote:
>>> On Thu, 26 Jun 2025 09:09:02 +0100,
>>> Yicong Yang wrote:
>
> [...]
>
>>>>
>>>
On 2025/6/26 16:51, Marc Zyngier wrote:
> On Thu, 26 Jun 2025 09:09:02 +0100,
> Yicong Yang wrote:
>>
>> From: Yicong Yang
>>
>> If FEAT_LS64WB not supported, FEAT_LS64* instructions only support
>> to access Device/Uncacheable memory, otherwise a data a
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