r_seq_state.attr,
&dev_attr_seq_event.attr,
Either ways, irrespective of the above comments :
Reviewed-by: Suzuki K Poulose
On 29/08/2019 22:33, Mike Leach wrote:
A number of issues are fixed relating to sysfs input validation:-
1) bb_ctrl_store() - incorrect compare of bit select field to absolute
value. Reworked per ETMv4 specification.
2) seq_event_store() - incorrect mask value - register has two
event values.
On 25/03/17 18:23, Leo Yan wrote:
Coresight includes debug module and usually the module connects with CPU
debug logic. ARMv8 architecture reference manual (ARM DDI 0487A.k) has
description for related info in "Part H: External Debug".
Chapter H7 "The Sample-based Profiling Extension" introduces
On 29/03/17 04:07, Leo Yan wrote:
Hi Suzuki,
On Mon, Mar 27, 2017 at 05:34:57PM +0100, Suzuki K Poulose wrote:
On 25/03/17 18:23, Leo Yan wrote:
[...]
Leo,
Thanks a lot for the quick rework. I don't fully understand (yet!) why we need
the
idle_constraint. I will leave it for Sude
On 29/03/17 11:27, Leo Yan wrote:
On Wed, Mar 29, 2017 at 10:07:07AM +0100, Suzuki K Poulose wrote:
[...]
+ if (mode == EDDEVID_IMPL_NONE) {
+ drvdata->edpcsr_present = false;
+ drvdata->edcidsr_present = false;
+ drvdata->edvids
On 29/03/17 11:37, Leo Yan wrote:
On Wed, Mar 29, 2017 at 11:31:03AM +0100, Suzuki K Poulose wrote:
On 29/03/17 11:27, Leo Yan wrote:
On Wed, Mar 29, 2017 at 10:07:07AM +0100, Suzuki K Poulose wrote:
[...]
+ if (mode == EDDEVID_IMPL_NONE) {
+ drvdata->edpcsr_pres
On 30/03/17 02:03, Leo Yan wrote:
On Wed, Mar 29, 2017 at 03:56:23PM +0100, Mike Leach wrote:
[...]
+ /*
+* Unfortunately the CPU cannot be powered up, so return
+* back and later has no permission to access other
+* registers. For this case, should set 'idle_constraint'
+* t
On 25/03/17 18:23, Leo Yan wrote:
This is refactor to add function of_coresight_get_cpu(), so it's used to
retrieve CPU id for coresight component. Finally can use it as a common
function for multiple places.
Suggested-by: Mathieu Poirier
Signed-off-by: Leo Yan
Reviewed-by: Suzuki K Po
Mike Leach
Reviewed-by: Mathieu Poirier
Signed-off-by: Leo Yan
Reviewed-by: Suzuki K Poulose
--
To unsubscribe from this list: send the line "unsubscribe linux-doc" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
On 06/04/17 14:30, Leo Yan wrote:
Coresight includes debug module and usually the module connects with CPU
debug logic. ARMv8 architecture reference manual (ARM DDI 0487A.k) has
description for related info in "Part H: External Debug".
Chapter H7 "The Sample-based Profiling Extension" introduces
On 19/04/17 15:28, Leo Yan wrote:
Hi Suzuki,
On Wed, Apr 19, 2017 at 02:23:04PM +0100, Suzuki K Poulose wrote:
Hi Leo,
This version looks good to me. I have two minor comments below.
Thanks for reviewing. Will take the suggestions. Just check a bit for
last comment.
[...]
+static int
and line parameter or sysfs
to constrain all or partial idle states to ensure the CPU power
domain is enabled and access coresight CPU debug component safely.
Signed-off-by: Leo Yan
With comments from Mathieu addressed,
Reviewed-by: Suzuki K Poulose
--
To unsubscribe from this list: send t
g unit on 96boards Hikey,
> Patch 0009 is to enable debug on 96boards DB410c. Have verified on both
> two boards.
Leo,
Please could you include the following patch in your series, which adds
the DT nodes for CPU debug on Juno boards ?
8>
From: Suzuki K Poulose
Date: Tue, 28 Mar
On 19/05/17 18:44, Sudeep Holla wrote:
Hi Suzuki, Leo,
On 19/05/17 05:25, Leo Yan wrote:
From: Suzuki K Poulose
Add Coresight CPU debug nodes for Juno r0, r1 & r2. The CPU
debug areas are mapped at the same address for all revisions,
like the ETM, even though the CPUs have changed from r
Hi gengdongjiu
Sorry for the late response. I have a similar patch to add the support
for "FHM", which I was about to post it this week.
On 11/12/17 13:29, Dave Martin wrote:
On Mon, Dec 11, 2017 at 08:47:00PM +0800, gengdongjiu wrote:
On 2017/12/11 19:59, Dave P Martin wrote:
On Sat, Dec
element in a third vector.
This patch detects this feature and let the userspace know about it via a
HWCAP bit and MRS emulation.
Cc: Dave Martin
Cc: Suzuki K Poulose
Signed-off-by: Dongjiu Geng
Reviewed-by: Dave Martin
Looks good to me.
Reviewed-by: Suzuki K Poulose
--
To unsubscribe from
Hi,
On 10/25/2018 06:59 AM, Kulkarni, Ganapatrao wrote:
This patch adds a perf driver for the PMU UNCORE devices DDR4 Memory
Controller(DMC) and Level 3 Cache(L3C). Each PMU supports up to 4
counters. All counters lack overflow interrupt and are
sampled periodically.
The patch looks OK overall
break;
+ i++;
+ }
+
+ return devices[i].type;
+}
+
+static bool tx2_uncore_validate_event(struct pmu *pmu,
+ struct perf_event *event, int *counters)
+{
+ if (is_software_event(event))
+ return true;
+ /* Reject groups spanning multiple HW PMUs. */
+ if (event->pmu != pmu)
+ return false;
+
+ *counters = *counters + 1;
+ return true;
nit: alignment.
Otherwise looks good to me.
FWIW, with the above nits fixed:
Reviewed-by: Suzuki K Poulose
Hi Jeremy
On 27/02/2019 01:05, Jeremy Linton wrote:
There are various reasons, including bencmarking, to disable spectrev2
mitigation on a machine. Provide a command-line to do so.
Signed-off-by: Jeremy Linton
Cc: Jonathan Corbet
Cc: linux-doc@vger.kernel.org
diff --git a/arch/arm64/kerne
On 28/02/2019 18:21, Catalin Marinas wrote:
On Thu, Feb 28, 2019 at 06:14:34PM +, Suzuki K Poulose wrote:
On 27/02/2019 01:05, Jeremy Linton wrote:
There are various reasons, including bencmarking, to disable spectrev2
mitigation on a machine. Provide a command-line to do so.
Signed
Hi Ganapatrao,
On 21/06/18 07:33, Ganapatrao Kulkarni wrote:
This patch adds a perf driver for the PMU UNCORE devices DDR4 Memory
Controller(DMC) and Level 3 Cache(L3C).
ThunderX2 has 8 independent DMC PMUs to capture performance events
corresponding to 8 channels of DDR4 Memory Controller and
Hi Ganapatrao,
On 11/10/18 07:39, Ganapatrao Kulkarni wrote:
+
+/*
+ * We must NOT create groups containing events from multiple hardware PMUs,
+ * although mixing different software and hardware PMUs is allowed.
+ */
+static bool thunderx2_uncore_validate_event_group(struct perf_event *event)
+
Hi Ganpatrao,
On 11/10/18 17:06, Ganapatrao Kulkarni wrote:
On Thu, Oct 11, 2018 at 2:43 PM Suzuki K Poulose wrote:
Hi Ganapatrao,
On 11/10/18 07:39, Ganapatrao Kulkarni wrote:
+
+/*
+ * We must NOT create groups containing events from multiple hardware PMUs,
+ * although mixing different
On 07/04/16 18:31, Marc Zyngier wrote:
+ All system register encodings above use the form
+
+ Op0, Op1, CRn, CRm, Op2.
+
+ Note that some of the encodings listed above include
+ the system register space reserved for the following
+ identification registers which ma
On 08/04/16 11:24, Marc Zyngier wrote:
On 08/04/16 10:58, Suzuki K Poulose wrote:
On 07/04/16 18:31, Marc Zyngier wrote:
+ All system register encodings above use the form
+
+ Op0, Op1, CRn, CRm, Op2.
+
+ Note that some of the encodings listed above include
+ the
On 31/03/2025 10:43, Yicong Yang wrote:
From: Yicong Yang
Instructions introduced by FEAT_{LS64, LS64_V} is controlled by
HCRX_EL2.{EnALS, EnASR}. Configure all of these to allow usage
at EL0/1.
This doesn't mean these instructions are always available in
EL0/1 if provided. The hypervisor stil
[] = {
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE,
ID_AA64DFR0_EL1_HPMN0_SHIFT, 4, 0),
This doesn't have to be FTR_STRICT. The kernel can deal with
differences, by skipping to use HPMN0. We anyway rely on the
system wide cap for using the feature.
Otherwise,
Acked-by: Suz
27 matches
Mail list logo
