On Thu, 29 Aug 2024 00:27:31 +0100,
Mark Brown wrote:
>
> GCS introduces a number of system registers for EL1 and EL0, on systems
> with GCS we need to context switch them and expose them to VMMs to allow
> guests to use GCS.
>
> In order to allow guests to use GCS we also need to configure
> HC
s Gleixner
Acked-by: Marc Zyngier
Given the various dependencies, I assume the series will get routed via
the MIPS tree.
Thanks,
M.
--
Jazz is not dead, it just smells funny...
On 11/01/17 18:06, Catalin Marinas wrote:
> Some minor comments below, nothing fundamental (as long as you say the
> new sequence doesn't have the speculative TLB load problem I mentioned
> on a previous version).
>
> On Wed, Jan 11, 2017 at 09:41:15AM -0500, Christopher Covington wrote:
>> diff -
[finally, some proper bikeshedding]
On 11/01/17 18:40, Timur Tabi wrote:
> On 01/11/2017 12:37 PM, Mark Rutland wrote:
>> The name, as it is, is perfectly descriptive.
>>
>> Let's not sacrifice legibility over a non-issue.
>
> I don't want to kick a dead horse or anything, but changing it to
> Q
On 31/01/17 17:48, Christopher Covington wrote:
> On 01/31/2017 07:37 AM, Mark Rutland wrote:
>> On Wed, Jan 25, 2017 at 10:52:30AM -0500, Christopher Covington wrote:
>>> The Qualcomm Datacenter Technologies Falkor v1 CPU may allocate TLB entries
>>> using an incorrect ASID when TTBRx_EL1 is being
On Wed, Feb 08 2017 at 2:09:12 pm GMT, Timur Tabi wrote:
> Mark Rutland wrote:
>
>>> No, only Kryo and Falkor V1 based SOCs have this problem. Falkor V2
>>> will have this fixed. We intend to revert these fixes after Falkor
>>> V1 SOCs are no longer supported.
>>
>> Supported by whom?
>
> Qualc
On Sun, Mar 05 2017 at 3:23:56 pm GMT, Shanker Donthineni
wrote:
> On Qualcomm Datacenter Technologies QDF2400 SoCs, the ITS hardware
> implementation uses 16Bytes for Interrupt Translation Entry (ITTE),
nit: Interrupt Translation Entry is abbreviated as ITE. I know the vITS
has the ITTE thing
Hi Amit,
On 22/03/17 05:38, Amit Kama IL wrote:
> Add initial support for boards based on Satixfy's SX3000b (Catniss) SoC.
> The SoC includes a MIPS interAptiv dual core 4 VPE processor and boots
> using device-tree.
>
> Signed-off-by: Amit Kama
>
> The irqchip file (irq-sx3000b.c) is pertinen
On 20/06/17 11:31, Bartosz Golaszewski wrote:
> 2017-05-31 18:06 GMT+02:00 Bartosz Golaszewski :
>> This series is a follow-up to [1].
>>
>> Some users of irq_alloc_generic_chip() are modules which can be
>> removed (e.g. gpio-ml-ioh) but have no means of freeing the allocated
>> generic chip.
>>
>
gt; kernel/irq/devres.c | 86
> +++
> kernel/irq/generic-chip.c | 7 ++-
> kernel/irq/internals.h | 11 +++++
> 5 files changed, 124 insertions(+), 4 deletions(-)
>
Looks OK to me. For the series:
Acked-
On 03/01/18 06:32, Ganapatrao Kulkarni wrote:
> When an interrupt is moved across node collections on ThunderX2
node collections?
> multi Socket platform, an interrupt stops routed to new collection
> and results in loss of interrupts.
>
> Adding workaround to issue INV after MOVI for cross-node
On 03/01/18 09:35, Ganapatrao Kulkarni wrote:
> Hi Marc,
>
> On Wed, Jan 3, 2018 at 2:17 PM, Marc Zyngier wrote:
>> On 03/01/18 06:32, Ganapatrao Kulkarni wrote:
>>> When an interrupt is moved across node collections on ThunderX2
>>
>> node collections?
&
On 03/01/18 11:20, Ganapatrao Kulkarni wrote:
> On Wed, Jan 3, 2018 at 3:43 PM, Marc Zyngier wrote:
>> On 03/01/18 09:35, Ganapatrao Kulkarni wrote:
>>> Hi Marc,
>>>
>>> On Wed, Jan 3, 2018 at 2:17 PM, Marc Zyngier wrote:
>>>> On 03/01/18 06:32, Ga
On 03/01/18 18:13, Ganapatrao Kulkarni wrote:
> On Wed, Jan 3, 2018 at 5:06 PM, Marc Zyngier wrote:
>> On 03/01/18 11:20, Ganapatrao Kulkarni wrote:
>>> On Wed, Jan 3, 2018 at 3:43 PM, Marc Zyngier wrote:
>>>> On 03/01/18 09:35, Ganapatrao Kulkarni wrote:
>>&g
On 18/01/18 05:28, Ganapatrao Kulkarni wrote:
> This erratum is observed on the ThunderX2 GICv3 ITS. When a
> MOVI command is used to change affinity of a LPI to a collection/cpu
> on another node, the LPI is not delivered to the cpu.
> An additional INV command is required after the MOVI to delive
On Sun, 21 Jan 2018 07:00:48 +,
Jayachandran C wrote:
>
> On Thu, Jan 18, 2018 at 10:58:20AM +0530, Ganapatrao Kulkarni wrote:
> > This erratum is observed on the ThunderX2 GICv3 ITS. When a
> > MOVI command is used to change affinity of a LPI to a collection/cpu
> > on another node, the LPI i
On Mon, 19 Feb 2018 21:12:10 +,
Jayachandran C wrote:
>
> On Sun, Jan 21, 2018 at 11:35:34AM +, Marc Zyngier wrote:
> > On Sun, 21 Jan 2018 07:00:48 +,
> > Jayachandran C wrote:
> > >
> > > On Thu, Jan 18, 2018 at 10:58:20AM +0530, Ganapatrao Kul
On 17/03/18 23:28, Paul Cercueil wrote:
> Add documentation about how to properly use the Ingenic TCU
> (Timer/Counter Unit) drivers from devicetree.
>
> Signed-off-by: Paul Cercueil
> ---
> .../bindings/clock/ingenic,tcu-clocks.txt | 42
> .../bindings/interrupt-contro
ister
> because it doesn't matter that kasan checks failed when
> unwind_pop_register read stack memory of task.
>
> Reviewed-by: Russell King - ARM Linux
> Reviewed-by: Florian Fainelli
> Reviewed-by: Marc Zyngier
Just because I replied to this patch doesn't mean yo
On 19/07/17 14:58, Thomas Gleixner wrote:
> On Wed, 19 Jul 2017, Bartosz Golaszewski wrote:
>
>> 2017-07-19 14:25 GMT+02:00 Thomas Gleixner :
>>> On Wed, 19 Jul 2017, Bartosz Golaszewski wrote:
>>>
Some frameworks (e.g. iio, gpiolib) use irq_work to implement simulated
interrupts that ca
On Tue, Sep 26 2017 at 9:45:42 pm BST, Yury Norov
wrote:
> Ping?
>
> On Wed, Sep 13, 2017 at 09:08:30PM +0300, Yury Norov wrote:
>> The Documentation/arm64/memory.txt says:
>> When using KVM, the hypervisor maps kernel pages in EL2, at a fixed
>> offset from the kernel VA (top 24bits of the kern
On Wed, Sep 27 2017 at 10:13:33 am BST, Will Deacon wrote:
> On Wed, Sep 27, 2017 at 09:31:41AM +0100, Marc Zyngier wrote:
>> On Tue, Sep 26 2017 at 9:45:42 pm BST, Yury Norov
>> wrote:
>> > On Wed, Sep 13, 2017 at 09:08:30PM +0300, Yury Norov wrote:
>> >>
xt | 12
> 1 file changed, 12 insertions(+)
Acked-by: Marc Zyngier
M.
--
Jazz is not dead. It just smells funny...
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HI Naveen,
On 07/04/16 16:54, Naveen Kaje wrote:
> The ARMv8.0 architecture reserves several system register
> encodings for future use. These encodings should behave
> as read-only and always return zero on a read. The Kryo core
> errantly causes an instruction abort upon an AArch64
> read attem
On 08/04/16 10:58, Suzuki K Poulose wrote:
> On 07/04/16 18:31, Marc Zyngier wrote:
>
>>> + All system register encodings above use the form
>>> +
>>> + Op0, Op1, CRn, CRm, Op2.
>>> +
>>> + Note that some of the encodings listed above inc
On 08/04/16 11:31, Suzuki K Poulose wrote:
> On 08/04/16 11:24, Marc Zyngier wrote:
>> On 08/04/16 10:58, Suzuki K Poulose wrote:
>>> On 07/04/16 18:31, Marc Zyngier wrote:
>>>
>>>>> + All system register encodings above use the form
>>>>>
On 21/04/16 18:40, Robert Richter wrote:
> On 15.04.16 21:30:05, Robert Richter wrote:
>> From: Ganapatrao Kulkarni
>>
>> The erratum fixes the hang of ITS SYNC command by avoiding inter node
>> io and collections/cpu mapping on thunderx dual-socket platform.
>>
>> This fix is only applicable for
On Thu, 10 Oct 2024 18:16:52 +0100,
Catalin Marinas wrote:
>
> On Thu, Oct 10, 2024 at 04:18:13PM +0100, Marc Zyngier wrote:
> > From 20c98d2647c11db1e40768f92c5998ff5d764a3a Mon Sep 17 00:00:00 2001
> > From: Marc Zyngier
> > Date: Thu, 10 Oct 2024 16:13:26 +0100
On Sat, 05 Oct 2024 15:26:38 +0100,
Mark Brown wrote:
>
> [1 ]
> On Sat, Oct 05, 2024 at 03:02:09PM +0100, Marc Zyngier wrote:
> > Mark Brown wrote:
>
> > > Ah, I see. I'd been under the impression that the generic machinery was
> > > supposed to hand
On Sat, 05 Oct 2024 15:14:21 +0100,
Mark Brown wrote:
>
> On Sat, Oct 05, 2024 at 01:36:09PM +0100, Marc Zyngier wrote:
> > Mark Brown wrote:
>
> > > + // PSTATE.EXLOCK is set to 0 upon any exception to a higher
> > > + // EL, or to GCSCR_ELx.EXLO
ation, but we're losing half of the space to the
vectors.
Anyway, this is very lightly tested and it may eat your box.
Thanks,
M.
From 20c98d2647c11db1e40768f92c5998ff5d764a3a Mon Sep 17 00:00:00 2001
From: Marc Zyngier
Date: Thu, 10 Oct 2024 16:13:26 +0100
Subject: [PATCH] KVM: arm64: Shave a few bytes fro
On Tue, 01 Oct 2024 23:58:55 +0100,
Mark Brown wrote:
> @@ -4714,6 +4735,10 @@ void kvm_calculate_traps(struct kvm_vcpu *vcpu)
> kvm->arch.fgu[HFGxTR_GROUP] |= (HFGxTR_EL2_nPOR_EL1 |
> HFGxTR_EL2_nPOR_EL0);
>
> + if (!kvm_has_gcs(k
On Wed, 02 Oct 2024 19:24:12 +0100,
Mark Brown wrote:
>
> [1 ]
> On Wed, Oct 02, 2024 at 04:55:25PM +0100, Marc Zyngier wrote:
> > Marc Zyngier wrote:
>
> > > > + if (!kvm_has_gcs(kvm))
> > > > + kvm->a
On Sat, 05 Oct 2024 11:37:30 +0100,
Mark Brown wrote:
>
> GCS introduces a number of system registers for EL1 and EL0, on systems
> with GCS we need to context switch them and expose them to VMMs to allow
> guests to use GCS.
>
> In order to allow guests to use GCS we also need to configure
> HC
On Sat, 05 Oct 2024 11:37:31 +0100,
Mark Brown wrote:
>
> As per DDI 0487 RWTXBY we need to manage PSTATE.EXLOCK when entering an
> exception, when the exception is entered from a lower EL the bit is cleared
> while if entering from the same EL it is set to GCSCR_ELx.EXLOCKEN.
> Implement this be
On Sat, 05 Oct 2024 14:08:39 +0100,
Mark Brown wrote:
>
> On Sat, Oct 05, 2024 at 12:34:20PM +0100, Marc Zyngier wrote:
> > Mark Brown wrote:
>
> > > + if (!kvm_has_gcs(kvm)) {
> > > + kvm->arch.fgu[H
On Sat, 05 Oct 2024 14:48:09 +0100,
Mark Brown wrote:
>
> [1 ]
> On Sat, Oct 05, 2024 at 02:18:57PM +0100, Marc Zyngier wrote:
> > Mark Brown wrote:
> > > On Sat, Oct 05, 2024 at 12:34:20PM +0100, Marc Zyngier wrote:
>
> > > > Where is the handling of tr
On Mon, 28 Oct 2024 20:24:17 +,
Mark Brown wrote:
>
> ID_AA64ISAR3_EL1 is currently marked as unallocated in KVM but does have a
> number of bitfields defined in it. Expose FPRCVT and FAMINMAX, two simple
> instruction only extensions to guests.
>
> Signed-off-by: Mark Brown
> ---
> arch/a
On Wed, 02 Oct 2024 01:24:25 +0100,
Marc Zyngier wrote:
>
> On Tue, 01 Oct 2024 23:58:55 +0100,
> Mark Brown wrote:
>
> > @@ -4714,6 +4735,10 @@ void kvm_calculate_traps(struct kvm_vcpu *vcpu)
> > kvm->arch.fgu[HFGxTR_GRO
Hi Mike,
Sorry for reviving a rather old thread.
On Wed, 07 Aug 2024 07:41:08 +0100,
Mike Rapoport wrote:
>
> From: "Mike Rapoport (Microsoft)"
>
> Until now arch_numa was directly translating firmware NUMA information
> to memblock.
>
> Using numa_memblks as an intermediate step has a few a
On Mon, 02 Dec 2024 13:55:04 +,
Yicong Yang wrote:
>
> From: Yicong Yang
>
> FEAT_LS64* instructions only support to access Device/Uncacheable
> memory, otherwise a data abort for unsupported Exclusive or atomic
Not quite. FEAT_LS64WB explicitly supports Write-Back mappings.
> access (0x3
On Mon, 02 Dec 2024 13:55:01 +,
Yicong Yang wrote:
>
> From: Yicong Yang
>
> Armv8.7 introduces single-copy atomic 64-byte loads and stores
> instructions and its variants named under FEAT_{LS64, LS64_V,
> LS64_ACCDATA}. These features are identified by ID_AA64ISAR1_EL1.LS64
> and the use o
rown
Reviewed-by: Marc Zyngier
M.
--
Without deviation from the norm, progress is not possible.
On Tue, 07 Jan 2025 16:42:38 +,
Will Deacon wrote:
>
> On Wed, 11 Dec 2024 01:02:45 +, Mark Brown wrote:
> > The 2024 architecture release includes a number of data processing
> > extensions, mostly SVE and SME additions with a few others. These are
> > all very straightforward extension
On Fri, 17 Jan 2025 11:34:09 +,
Mark Rutland wrote:
>
> On Fri, Dec 20, 2024 at 04:46:34PM +, Mark Brown wrote:
> > The SVE portion of kvm_vcpu_put() is quite large, especially given the
> > comments required. When we add similar handling for SME the function
> > will get even larger, in
On Fri, 14 Feb 2025 01:57:43 +,
Mark Brown wrote:
>
> I've removed the RFC tag from this version of the series, but the items
> that I'm looking for feedback on remains the same:
>
> - The userspace ABI, in particular:
> - The vector length used for the SVE registers, access to the SVE
>
On Fri, 14 Feb 2025 15:13:52 +,
Mark Brown wrote:
>
> On Fri, Feb 14, 2025 at 09:24:03AM +, Marc Zyngier wrote:
> > Mark Brown wrote:
>
> > Just to be clear: I do not intend to review a series that doesn't
> > cover the full gamut of KVM from day
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