On 2/10/2025 10:12 AM, Jie Gan wrote:
+static int ppe_clock_init_and_reset(struct ppe_device *ppe_dev)
+{
+ unsigned long ppe_rate = ppe_dev->clk_rate;
+ struct device *dev = ppe_dev->dev;
+ struct reset_control *rstc;
+ struct clk_bulk_data *clks;
+ struct clk *clk;
+ int re
On 2/10/2025 10:47 AM, Jie Gan wrote:
diff --git a/Documentation/devicetree/bindings/net/qcom,ipq9574-
ppe.yaml b/Documentation/devicetree/bindings/net/qcom,ipq9574-ppe.yaml
new file mode 100644
index ..be6f9311eebb
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/qcom,ip
On 1/10/2025 1:52 AM, Simon Horman wrote:
On Wed, Jan 08, 2025 at 09:47:14PM +0800, Luo Jie wrote:
Configure unicast and multicast hardware queues for the PPE
ports to enable packet forwarding between the ports.
Each PPE port is assigned with a range of queues. The queue ID
selection for a p
On 1/10/2025 4:11 AM, Simon Horman wrote:
On Thu, Jan 09, 2025 at 05:27:14PM +, Simon Horman wrote:
On Wed, Jan 08, 2025 at 09:47:11PM +0800, Luo Jie wrote:
The BM (Buffer Management) config controls the pause frame generated
on the PPE port. There are maximum 15 BM ports and 4 groups su
On 1/10/2025 1:42 AM, Simon Horman wrote:
On Wed, Jan 08, 2025 at 09:47:13PM +0800, Luo Jie wrote:
The PPE scheduler settings determine the priority of scheduling the
packet across the different hardware queues per PPE port.
Signed-off-by: Luo Jie
---
drivers/net/ethernet/qualcomm/ppe/ppe
On 1/9/2025 5:15 PM, Krzysztof Kozlowski wrote:
On Wed, Jan 08, 2025 at 09:47:08PM +0800, Luo Jie wrote:
+required:
+ - clocks
+ - clock-names
+ - resets
+ - interrupts
+ - interrupt-names
+
+ ethernet-ports:
This device really looks like DSA or other ethernet
On 1/10/2025 1:58 AM, Simon Horman wrote:
On Wed, Jan 08, 2025 at 09:47:15PM +0800, Luo Jie wrote:
PPE service code is a special code (0-255) that is defined by PPE for
PPE's packet processing stages, as per the network functions required
for the packet.
For packet being sent out by ARM core
On 1/9/2025 3:27 AM, Christophe JAILLET wrote:
Le 08/01/2025 à 14:47, Luo Jie a écrit :
The PPE scheduler settings determine the priority of scheduling the
packet across the different hardware queues per PPE port.
Signed-off-by: Luo Jie
...
+/* Scheduler configuration for dispatching pa
On 1/9/2025 3:29 AM, Christophe JAILLET wrote:
Le 08/01/2025 à 14:47, Luo Jie a écrit :
Configure unicast and multicast hardware queues for the PPE
ports to enable packet forwarding between the ports.
Each PPE port is assigned with a range of queues. The queue ID
selection for a packet is de
On 1/9/2025 3:19 AM, Christophe JAILLET wrote:
Le 08/01/2025 à 14:47, Luo Jie a écrit :
The PPE (Packet Process Engine) hardware block is available
on Qualcomm IPQ SoC that support PPE architecture, such as
IPQ9574.
The PPE in IPQ9574 includes six integrated ethernet MAC
(for 6 PPE ports), b
On 1/9/2025 12:43 AM, Andrew Lunn wrote:
On Wed, Jan 08, 2025 at 09:47:20PM +0800, Luo Jie wrote:
The PPE hardware packet counters are made available through
the debugfs entry "/sys/kernel/debug/ppe/packet_counters".
Why?
Would it not be better to make them available via ethtool -S ?
Man
On 2/12/2025 9:58 AM, Jie Gan wrote:
+static int qcom_ppe_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct ppe_device *ppe_dev;
+ void __iomem *base;
+ int ret, num_icc;
I think it's better with:
int num_icc = ARRAY_SIZE(ppe_icc_data);
This
On 2/11/2025 9:14 PM, Andrew Lunn wrote:
+/* Assign the share buffer number 1550 to group 0 by default. */
+static const int ipq9574_ppe_bm_group_config = 1550;
To a large extent, the comment is useless. What should be in the
comment is why, not what.
Andrew
OK, I will improve th
On 2/20/2025 11:09 PM, Andrew Lunn wrote:
On Thu, Feb 20, 2025 at 10:38:03PM +0800, Jie Luo wrote:
On 2/11/2025 9:22 PM, Andrew Lunn wrote:
+ /* Configure BM flow control related threshold. */
+ PPE_BM_PORT_FC_SET_WEIGHT(bm_fc_val, port_cfg.weight
On 3/6/2025 11:29 PM, Andrew Lunn wrote:
Thanks for the suggestion. Just to clarify, we preferred
u32p_replace_bits() over FIELD_PREP() because the former does
a clear-and-set operation against a given mask, where as with
FIELD_PREP(), we need to clear the bits first before we use the
macro an
On 2/20/2025 11:12 PM, Andrew Lunn wrote:
As a general rule, we have tried to keep the data structure definition
accurately mirror the hardware table design, for easier understanding
and debug ability of the code.
Could you point me at the datasheet which describes the table?
Andrew
On 2/11/2025 9:55 PM, Andrew Lunn wrote:
+#define PRINT_COUNTER_PREFIX(desc, cnt_type) \
+ seq_printf(seq, "%-16s %16s", desc, cnt_type)
+
+#define PRINT_CPU_CODE_COUNTER(cnt, code) \
+ seq_printf(seq, "%10u(cpucode:%d)", cnt, code)
+
+#define PRINT_DROP_CODE
On 2/11/2025 9:22 PM, Andrew Lunn wrote:
+ /* Configure BM flow control related threshold. */
+ PPE_BM_PORT_FC_SET_WEIGHT(bm_fc_val, port_cfg.weight);
+ PPE_BM_PORT_FC_SET_RESUME_OFFSET(bm_fc_val, port_cfg.resume_offset);
+ PPE_BM_PORT_FC_SET_RESUME_THRESHOLD(bm_fc_val,
On 2/11/2025 9:32 PM, Andrew Lunn wrote:
+/* Scheduler configuration for the assigning and releasing buffers for the
+ * packet passing through PPE, which is different per SoC.
+ */
+static const struct ppe_scheduler_bm_config ipq9574_ppe_sch_bm_config[] = {
+ {1, 0, 0, 0, 0},
+ {1
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