On Mon, Sep 02, 2024 at 07:58:28PM +0100, Mark Brown wrote:
> On Mon, Sep 02, 2024 at 07:56:32PM +0100, Catalin Marinas wrote:
> > On Thu, Aug 29, 2024 at 12:27:42AM +0100, Mark Brown wrote:
>
> > > +static int gcs_get(struct task_struct *target,
> > > +
Hi,
I know Will is on the case but just expressing some thoughts of my own.
On Mon, Jun 17, 2019 at 11:32:54PM +0900, Takao Indoh wrote:
> From: Takao Indoh
>
> mm_cpumask was deleted by the commit 38d96287504a ("arm64: mm: kill
> mm_cpumask usage") because it was not used at that time. Now thi
On Mon, Jun 17, 2019 at 11:32:55PM +0900, Takao Indoh wrote:
> From: Takao Indoh
>
> This patch adds new boot parameter 'disable_tlbflush_is' to disable TLB
> flush within the same inner shareable domain for performance tuning.
>
> In the case of flush_tlb_mm() *without* this parameter, TLB entr
Hi Dave,
On Wed, Jul 31, 2019 at 09:43:46AM -0700, Dave Hansen wrote:
> On 7/25/19 6:50 AM, Vincenzo Frascino wrote:
> > With the relaxed ABI proposed through this document, it is now possible
> > to pass tagged pointers to the syscalls, when these pointers are in
> > memory ranges obtained by an
Hi,
Thanks for the feedback so far. This is an updated series documenting
the AArch64 Tagged Address ABI as implemented by these patches:
http://lkml.kernel.org/r/cover.1563904656.git.andreyk...@google.com
Version 6 of the documentation series is available here:
http://lkml.kernel.org/r/2019072
prctl() can be used
in combination to allow the userspace to opt-in this feature.
Cc: Will Deacon
Cc: Andrey Konovalov
Cc: Szabolcs Nagy
Cc: Kevin Brodsky
Signed-off-by: Vincenzo Frascino
[catalin.mari...@arm.com: some rewording, dropped MAP_PRIVATE]
Signed-off-by: Catalin Marinas
: Andrey Konovalov
Cc: Szabolcs Nagy
Cc: Kevin Brodsky
Signed-off-by: Vincenzo Frascino
[catalin.mari...@arm.com: minor tweaks]
Signed-off-by: Catalin Marinas
---
Documentation/arm64/tagged-pointers.rst | 23 ---
1 file changed, 16 insertions(+), 7 deletions(-)
diff --git a
On Wed, Aug 07, 2019 at 01:38:16PM -0700, Dave Hansen wrote:
> On 8/7/19 8:53 AM, Catalin Marinas wrote:
> > +- mmap() done by the process itself (or its parent), where either:
> > +
> > + - flags have the **MAP_ANONYMOUS** bit set
> > + - the file descriptor refers t
On Mon, Aug 12, 2019 at 11:46:06AM +0100, Andrew Murray wrote:
> On Thu, Aug 08, 2019 at 06:04:24PM +0100, Will Deacon wrote:
> > On Wed, Aug 07, 2019 at 04:53:20PM +0100, Catalin Marinas wrote:
> > > +
> > > +- mmap() addr parameter.
> > > +
>
On Fri, Aug 09, 2019 at 07:10:18AM -0700, Dave Hansen wrote:
> On 8/8/19 10:27 AM, Catalin Marinas wrote:
> > On Wed, Aug 07, 2019 at 01:38:16PM -0700, Dave Hansen wrote:
> >> Also, shouldn't this be converted over to an arch_prctl()?
> >
> > What do you mean
even without the prctl()
opt-in, the tag is still ignored on a few syscalls (untagged_addr() in
the kernel is unconditional)
- compilable example code together with syscall use
- added a note on tag preservation in the tagged-pointers.rst document
- various rewordings and cleanups
Catalin Ma
There isn't a good reason to differentiate between the user address
space layout modification syscalls and the other memory
permission/attributes ones (e.g. mprotect, madvise) w.r.t. the tagged
address ABI. Untag the user addresses on entry to these functions.
Signed-off-by: Catalin Ma
-off-by: Catalin Marinas
---
arch/arm64/kernel/process.c | 17 ++---
1 file changed, 10 insertions(+), 7 deletions(-)
diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c
index 76b7c55026aa..03689c0beb34 100644
--- a/arch/arm64/kernel/process.c
+++ b/arch/arm64
Frascino
Co-developed-by: Catalin Marinas
Signed-off-by: Catalin Marinas
---
Documentation/arm64/tagged-pointers.rst | 23 ---
1 file changed, 16 insertions(+), 7 deletions(-)
diff --git a/Documentation/arm64/tagged-pointers.rst
b/Documentation/arm64/tagged-pointers.rst
pointers to
kernel syscalls.
Cc: Will Deacon
Cc: Andrey Konovalov
Cc: Szabolcs Nagy
Cc: Kevin Brodsky
Signed-off-by: Vincenzo Frascino
Co-developed-by: Catalin Marinas
Signed-off-by: Catalin Marinas
---
Documentation/arm64/tagged-address-abi.rst | 155 +
1 file changed, 155
Require that arg{3,4,5} of the PR_{SET,GET}_TAGGED_ADDR_CTRL prctl and
arg2 of the PR_GET_TAGGED_ADDR_CTRL prctl() are zero rather than ignored
for future extensions.
Signed-off-by: Catalin Marinas
---
kernel/sys.c | 4
1 file changed, 4 insertions(+)
diff --git a/kernel/sys.c b/kernel
: Vincenzo Frascino
Co-developed-by: Catalin Marinas
Signed-off-by: Catalin Marinas
---
Documentation/arm64/tagged-pointers.rst | 23 ---
1 file changed, 16 insertions(+), 7 deletions(-)
diff --git a/Documentation/arm64/tagged-pointers.rst
b/Documentation/arm64/tagged
pointers to
kernel syscalls.
Cc: Will Deacon
Cc: Andrey Konovalov
Cc: Szabolcs Nagy
Cc: Kevin Brodsky
Signed-off-by: Vincenzo Frascino
Co-developed-by: Catalin Marinas
Signed-off-by: Catalin Marinas
---
Documentation/arm64/tagged-address-abi.rst | 156 +
1 file changed, 156
ed-by: Andrey Konovalov
Signed-off-by: Catalin Marinas
---
mm/mmap.c | 5 +
mm/mremap.c | 6 +-
2 files changed, 6 insertions(+), 5 deletions(-)
diff --git a/mm/mmap.c b/mm/mmap.c
index 7e8c3e8ae75f..b766b633b7ae 100644
--- a/mm/mmap.c
+++ b/mm/mmap.c
@@ -201,6 +201,8 @@ SYSCALL_DEFINE
pointers
- Reworded the prctl/ioctl restrictions to clarify the allowed tagged
pointers w.r.t. user data access by the kernel
Catalin Marinas (1):
mm: untag user pointers in mmap/munmap/mremap/brk
Vincenzo Frascino (2):
arm64: Define Documentation/arm64/tagged-address-abi.rst
arm64: Relax Docum
On Wed, Aug 21, 2019 at 07:46:51PM +0100, Dave P Martin wrote:
> On Wed, Aug 21, 2019 at 06:33:53PM +0100, Will Deacon wrote:
> > On Wed, Aug 21, 2019 at 05:47:30PM +0100, Catalin Marinas wrote:
> > > @@ -59,6 +63,11 @@ be preserved.
> > > The architecture prevents the
On Thu, Aug 22, 2019 at 05:37:23PM +0100, Dave P Martin wrote:
> On Thu, Aug 22, 2019 at 04:55:32PM +0100, Catalin Marinas wrote:
> > On Wed, Aug 21, 2019 at 07:46:51PM +0100, Dave P Martin wrote:
> > > On Wed, Aug 21, 2019 at 06:33:53PM +0100, Will Deacon wrote:
> > > &
Hi,
Minor update to the arm64 tagged address ABI documentation since v9,
posted here:
http://lkml.kernel.org/r/20190821164730.47450-1-catalin.mari...@arm.com
The mmap/mremap/... patch (1/3) has been queued in the -mm tree and
removed from this series. The tagged-address-abi.rst patch (2/3) has
b
: Vincenzo Frascino
Co-developed-by: Catalin Marinas
Signed-off-by: Catalin Marinas
---
Documentation/arm64/tagged-pointers.rst | 21 ++---
1 file changed, 14 insertions(+), 7 deletions(-)
diff --git a/Documentation/arm64/tagged-pointers.rst
b/Documentation/arm64/tagged
lect that.
>
> Signed-off-by: Jeremy Cline
I forgot about this. Thanks.
Acked-by: Catalin Marinas
On Fri, Oct 04, 2019 at 11:37:22AM +0100, Will Deacon wrote:
> On Thu, Oct 03, 2019 at 12:12:07PM +0100, Julien Grall wrote:
> > This patch fix an issue related to exposing the FRINT capability to
> > userspace (see patch #1). The rest is documentation update.
> >
> For patches 2-4:
>
> Acked-by:
Hi Ionela,
On Tue, Sep 17, 2019 at 02:42:25PM +0100, Ionela Voinescu wrote:
> +#ifdef CONFIG_ARM64_AMU_EXTN
> +
> +/*
> + * This per cpu variable only signals that the CPU implementation supports
> the
> + * AMU but does not provide information regarding all the events that it
> + * supports.
> +
On Fri, Oct 11, 2019 at 11:31:40AM +0100, Ionela Voinescu wrote:
> On 10/10/2019 18:20, Catalin Marinas wrote:
> > On Tue, Sep 17, 2019 at 02:42:25PM +0100, Ionela Voinescu wrote:
> >> +#ifdef CONFIG_ARM64_AMU_EXTN
> >> +
> >> +/*
> >> + * Th
Hi Vincenzo,
Some minor comments below but it looks fine to me overall. Cc'ing
Szabolcs as well since I'd like a view from the libc people.
On Wed, Jun 12, 2019 at 03:21:10PM +0100, Vincenzo Frascino wrote:
> diff --git a/Documentation/arm64/tagged-address-abi.txt
> b/Documentation/arm64/tagged-
A couple of minor nits below.
On Wed, Jun 12, 2019 at 03:21:11PM +0100, Vincenzo Frascino wrote:
> --- a/Documentation/arm64/tagged-pointers.txt
> +++ b/Documentation/arm64/tagged-pointers.txt
> @@ -18,7 +18,8 @@ Passing tagged addresses to the kernel
> --
>
On Thu, Jun 13, 2019 at 12:37:32PM +0100, Dave P Martin wrote:
> On Thu, Jun 13, 2019 at 11:15:34AM +0100, Vincenzo Frascino wrote:
> > On 12/06/2019 16:35, Catalin Marinas wrote:
> > > On Wed, Jun 12, 2019 at 03:21:10PM +0100, Vincenzo Frascino wrote:
> > >> + - P
On Thu, Jun 13, 2019 at 02:23:43PM +0100, Dave P Martin wrote:
> On Thu, Jun 13, 2019 at 01:28:21PM +0100, Catalin Marinas wrote:
> > On Thu, Jun 13, 2019 at 12:37:32PM +0100, Dave P Martin wrote:
> > > On Thu, Jun 13, 2019 at 11:15:34AM +0100, Vincenzo Frascino wrote:
> >
Hi Szabolcs,
On Wed, Jun 12, 2019 at 05:30:34PM +0100, Szabolcs Nagy wrote:
> On 12/06/2019 15:21, Vincenzo Frascino wrote:
> > +2. ARM64 Tagged Address ABI
> > +---
> > +
> > +From the kernel syscall interface prospective, we define, for the purposes
>
On Tue, Jun 18, 2019 at 02:13:01PM +0100, Kevin Brodsky wrote:
> On 13/06/2019 16:51, Vincenzo Frascino wrote:
> > +The ARM64 Tagged Address ABI is an opt-in feature, and an application can
> > +control it using the following:
> > + - /proc/sys/abi/tagged_addr: a new sysctl interface that can be us
On Fri, Jan 06, 2017 at 02:10:03AM +0530, Yury Norov wrote:
> On Wed, Dec 07, 2016 at 09:40:13PM +0100, Arnd Bergmann wrote:
> > On Wednesday, December 7, 2016 4:59:13 PM CET Catalin Marinas wrote:
> > > On Tue, Dec 06, 2016 at 11:55:08AM +0530, Yury Norov wrote:
> > > &
On Sun, Dec 18, 2016 at 12:38:23PM +0530, Yury Norov wrote:
> On Fri, Oct 21, 2016 at 11:32:59PM +0300, Yury Norov wrote:
> > This series enables aarch64 with ilp32 mode, and as supporting work,
> > introduces ARCH_32BIT_OFF_T configuration option that is enabled for
> > existing 32-bit architectur
On Thu, Dec 22, 2016 at 12:26:40AM +0530, Yury Norov wrote:
> On Mon, Dec 05, 2016 at 03:38:01PM +0000, Catalin Marinas wrote:
> > On Fri, Oct 21, 2016 at 11:33:09PM +0300, Yury Norov wrote:
> > > binfmt_ilp32.c is needed to handle ILP32 binaries
> > >
>
Some minor comments below, nothing fundamental (as long as you say the
new sequence doesn't have the speculative TLB load problem I mentioned
on a previous version).
On Wed, Jan 11, 2017 at 09:41:15AM -0500, Christopher Covington wrote:
> diff --git a/Documentation/arm64/silicon-errata.txt
> b/Do
On Wed, Jan 11, 2017 at 06:37:39PM +, Mark Rutland wrote:
> On Wed, Jan 11, 2017 at 12:35:55PM -0600, Timur Tabi wrote:
> > On 01/11/2017 12:33 PM, Mark Rutland wrote:
> > >It'll need to affect all lines since the kconfig column needs to expand
> > >by at least one character to fit QCOM_FALKOR_
On Wed, Jan 11, 2017 at 06:40:52PM +, Mark Rutland wrote:
> On Wed, Jan 11, 2017 at 06:22:08PM +, Marc Zyngier wrote:
> > On 11/01/17 18:06, Catalin Marinas wrote:
> > > On Wed, Jan 11, 2017 at 09:41:15AM -0500, Christopher Covington wrote:
> > >> diff --git
On Wed, Jan 11, 2017 at 06:22:08PM +, Marc Zyngier wrote:
> On 11/01/17 18:06, Catalin Marinas wrote:
> > On Wed, Jan 11, 2017 at 09:41:15AM -0500, Christopher Covington wrote:
> >> diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S
> >> index 32682be..9ee
On Wed, Feb 01, 2017 at 04:33:58PM +, Will Deacon wrote:
> On Wed, Feb 01, 2017 at 11:29:22AM -0500, Christopher Covington wrote:
> > On 01/31/2017 12:56 PM, Marc Zyngier wrote:
> > > Given that all ARMv8 CPUs can support SW_PAN, it is more likely to be
> > > enabled than the ARMv8.1 PAN. I'd v
On Wed, Feb 01, 2017 at 05:41:05PM +, Will Deacon wrote:
> On Wed, Feb 01, 2017 at 05:36:09PM +0000, Catalin Marinas wrote:
> > On Wed, Feb 01, 2017 at 04:33:58PM +, Will Deacon wrote:
> > > On Wed, Feb 01, 2017 at 11:29:22AM -0500, Christopher Covington wrote:
> >
On Wed, Feb 01, 2017 at 05:49:34PM +, Catalin Marinas wrote:
> On Wed, Feb 01, 2017 at 05:41:05PM +, Will Deacon wrote:
> > On Wed, Feb 01, 2017 at 05:36:09PM +, Catalin Marinas wrote:
> > > On Wed, Feb 01, 2017 at 04:33:58PM +, Will Deacon wrote:
> > > &
On Wed, Feb 01, 2017 at 05:59:48PM +, Will Deacon wrote:
> On Wed, Feb 01, 2017 at 05:49:34PM +0000, Catalin Marinas wrote:
> > On Wed, Feb 01, 2017 at 05:41:05PM +, Will Deacon wrote:
> > > On Wed, Feb 01, 2017 at 05:36:09PM +0000, Catalin Marinas wrote:
> > > &
On Wed, Feb 01, 2017 at 06:34:01PM +, Will Deacon wrote:
> On Wed, Feb 01, 2017 at 06:22:44PM +0000, Catalin Marinas wrote:
> > On Wed, Feb 01, 2017 at 05:59:48PM +, Will Deacon wrote:
> > > On Wed, Feb 01, 2017 at 05:49:34PM +0000, Catalin Marinas wrote:
> > > &
On Tue, Feb 07, 2017 at 07:35:16PM -0500, Christopher Covington wrote:
> --- a/arch/arm64/Kconfig
> +++ b/arch/arm64/Kconfig
> @@ -480,6 +480,18 @@ config CAVIUM_ERRATUM_27456
>
> If unsure, say Y.
>
> +config QCOM_FALKOR_ERRATUM_1003
> + bool "Falkor E1003: Incorrect translation du
e reserved
> ASID. Yet this will not reduce functionality, since TLB entries incorrectly
> tagged with the reserved ASID will never be hit by a later instruction.
>
> Based on work by Shanker Donthineni
>
> Signed-off-by: Christopher Covington
Reviewed-by: Catalin Marinas
On Mon, Apr 10, 2017 at 11:47:40PM +0400, Yury Norov wrote:
> According to latest plans figured out on Linaro Connect, ILP32 should
> be taken in 4.12 merge window.
Sorry, I wasn't present at Linaro Connect, so definitely not involved in
such decision.
BTW, it would be nice to have Arnd's ack on
On Sun, Jun 04, 2017 at 02:59:54PM +0300, Yury Norov wrote:
> --- a/arch/arm64/Kconfig
> +++ b/arch/arm64/Kconfig
> @@ -402,7 +402,7 @@ config ARM64_ERRATUM_834220
>
> config ARM64_ERRATUM_845719
> bool "Cortex-A53: 845719: a load might read incorrect data"
> - depends on COMPAT
> +
On Sun, Jun 04, 2017 at 03:00:02PM +0300, Yury Norov wrote:
> off_t is passed in register pair just like in aarch32.
> In this patch corresponding aarch32 handlers are shared to
> ilp32 code.
Is the comment here relevant? IOW, do we have any AArch64/ILP32 syscall
where off_t is used as an argumen
On Sun, Jun 04, 2017 at 02:59:51PM +0300, Yury Norov wrote:
> All new 32-bit architectures should have 64-bit off_t type, but existing
> architectures has 32-bit ones.
>
> To handle it, new config option is added to arch/Kconfig that defaults
> ARCH_32BIT_OFF_T to be disabled for non-64 bit archit
On Sun, Jun 04, 2017 at 03:00:08PM +0300, Yury Norov wrote:
> From: Philipp Tomsich
>
> ILP32 VDSO exports following symbols:
> __kernel_rt_sigreturn;
> __kernel_gettimeofday;
> __kernel_clock_gettime;
> __kernel_clock_getres.
>
> What shared object to use, kernel selects depending on result
On Fri, Jun 09, 2017 at 01:40:59AM +0300, Yury Norov wrote:
> On Thu, Jun 08, 2017 at 03:09:12PM +0100, Catalin Marinas wrote:
> > On Sun, Jun 04, 2017 at 02:59:54PM +0300, Yury Norov wrote:
> > > --- a/arch/arm64/Kconfig
> > > +++ b/arch/arm64/Kconfig
>
On Tue, Jun 13, 2017 at 02:04:11PM +0300, Yury Norov wrote:
> On Thu, Jun 08, 2017 at 04:09:50PM +0100, Catalin Marinas wrote:
> > On Sun, Jun 04, 2017 at 02:59:51PM +0300, Yury Norov wrote:
> > > All new 32-bit architectures should have 64-bit off_t type, but existing
> >
Hi Yury,
On Mon, Jun 19, 2017 at 06:49:43PM +0300, Yury Norov wrote:
> This series enables aarch64 with ilp32 mode.
Thanks for putting this series together, I do appreciate the effort.
There are still some review comments coming in but I'm happy with how
the ABI looks now. I did some LTP testing
Hi Yury,
Just a quick reply as I'm about to go on holiday for the next two weeks.
On Fri, Jul 07, 2017 at 12:59:02AM +0300, Yury Norov wrote:
> On Thu, Jun 29, 2017 at 05:10:36PM +0100, Catalin Marinas wrote:
> > On Mon, Jun 19, 2017 at 06:49:43PM +0300, Yury Norov wrote:
>
Hi Yury,
On Thu, Nov 16, 2017 at 02:11:30PM +0300, Yury Norov wrote:
> This is ILP32 patches on top of 4.14 kernel:
> https://github.com/norov/linux/commits/ilp32-4.14
>
> I tested the series with LTP lite built by Linaro toolchain, and no
> regressions found.
Thanks. I gave it a try as well wit
On Fri, Jan 05, 2018 at 04:22:24PM +0800, gengdongjiu wrote:
> On 2018/1/5 15:57, Greg KH wrote:
> > On Fri, Jan 05, 2018 at 09:22:54AM +0800, gengdongjiu wrote:
> >> Hi will/catalin
> >>
> >> On 2017/12/13 18:09, Suzuki K Poulose wrote:
> >>> On 13/12/17 10:13, Dongjiu Geng wrote:
> ARM v8.4
Hi Andrey,
On Thu, Nov 08, 2018 at 03:48:10PM +0100, Andrey Konovalov wrote:
> On Thu, Nov 8, 2018 at 3:36 PM, Andrey Konovalov
> wrote:
> > Changes in v8:
> > - Rebased onto 65102238 (4.20-rc1).
> > - Added a note to the cover letter on why syscall wrappers/shims that untag
> > user pointers
(), for instance.
> */
> -#define untagged_addr(addr) sign_extend64(addr, 55)
> +#define untagged_addr(addr) \
> + ((__typeof__(addr))sign_extend64((__u64)(addr), 55))
Nitpick: same comment as here (use u64):
http://lkml.kernel.org/r/20181123173739.osgvnnhmpt
clude
>
> +#ifndef untagged_addr
> +#define untagged_addr(addr) addr
> +#endif
Nitpick: add braces around (addr). Otherwise:
Acked-by: Catalin Marinas
ser,
> we need to correctly handle such pointers.
>
> Do this by untagging user pointers in access_ok and in __uaccess_mask_ptr,
> before performing access validity checks.
>
> Signed-off-by: Andrey Konovalov
Reviewed-by: Catalin Marinas
On Thu, Dec 06, 2018 at 01:44:24PM +0100, Andrey Konovalov wrote:
> On Thu, Nov 29, 2018 at 7:16 PM Catalin Marinas
> wrote:
> > On Thu, Nov 08, 2018 at 03:48:10PM +0100, Andrey Konovalov wrote:
> > > On Thu, Nov 8, 2018 at 3:36 PM, Andrey Konovalov
> > >
Hi Andrey,
On Wed, Dec 12, 2018 at 03:23:25PM +0100, Andrey Konovalov wrote:
> On Mon, Dec 10, 2018 at 3:31 PM Vincenzo Frascino
> wrote:
> > On arm64 the TCR_EL1.TBI0 bit has been set since Linux 3.x hence
> > the userspace (EL0) is allowed to set a non-zero value in the top
> > byte but the res
On Tue, Dec 18, 2018 at 04:03:38PM +0100, Andrey Konovalov wrote:
> On Wed, Dec 12, 2018 at 4:02 PM Catalin Marinas
> wrote:
> > The summary of our internal discussions (mostly between kernel
> > developers) is that we can't properly describe a user ABI that covers
> &g
Hi Dave,
On Wed, Dec 12, 2018 at 05:01:12PM +, Dave P Martin wrote:
> On Mon, Dec 10, 2018 at 01:50:57PM +0100, Andrey Konovalov wrote:
> > arm64 has a feature called Top Byte Ignore, which allows to embed pointer
> > tags into the top byte of each pointer. Userspace programs (such as
> > HWAS
On Mon, Feb 11, 2019 at 12:32:55PM -0800, Evgenii Stepanov wrote:
> On Mon, Feb 11, 2019 at 9:28 AM Kevin Brodsky wrote:
> > On 19/12/2018 12:52, Dave Martin wrote:
> > > Really, the kernel should do the expected thing with all "non-weird"
> > > memory.
> > >
> > > In lieu of a proper definition o
Hi Szabolcs,
Thanks for looking into this. Comments below.
On Tue, Feb 19, 2019 at 06:38:31PM +, Szabolcs Nagy wrote:
> i think these rules work for the cases i care about, a more
> tricky question is when/how to check for the new syscall abi
> and when/how the TCR_EL1.TBI0 setting may be tur
On Thu, Feb 28, 2019 at 06:14:34PM +, Suzuki K Poulose wrote:
> On 27/02/2019 01:05, Jeremy Linton wrote:
> > There are various reasons, including bencmarking, to disable spectrev2
> > mitigation on a machine. Provide a command-line to do so.
> >
> > Signed-off-by: Jeremy Linton
> > Cc: Jonat
On Tue, Feb 26, 2019 at 03:39:08PM +0100, Andrey Konovalov wrote:
> On Sat, Feb 23, 2019 at 12:06 AM Dave Hansen wrote:
> >
> > On 2/22/19 4:53 AM, Andrey Konovalov wrote:
> > > userfaultfd_register() and userfaultfd_unregister() use provided user
> > > pointers for vma lookups, which can only by
On Mon, Jul 24, 2017 at 05:16:34PM +0800, shuw...@redhat.com wrote:
> When running memory stress tests, kmemleak could be easily disabled in
> function create_object as system is out of memory and kmemleak failed to
> alloc from object_cache. Since there's no way to enable kmemleak after
> it's off
Hi Yury,
On Mon, Jul 24, 2017 at 02:26:24PM +0300, Yury Norov wrote:
> On Fri, Jul 07, 2017 at 06:11:36PM +0100, Catalin Marinas wrote:
> > On Fri, Jul 07, 2017 at 12:59:02AM +0300, Yury Norov wrote:
> > > If so, I would like to ask you to do the first ILP32 community poll
&
On Mon, Jul 24, 2017 at 02:26:24PM +0300, Yury Norov wrote:
> This is the 4.12 and linux-next - based kernel patches:
> https://github.com/norov/linux/tree/ilp32-4.12
> https://github.com/norov/linux/tree/ilp32-20170724
I published the 4.12 branch here:
https://git.kernel.org/pub/scm/linux/kernel
On Mon, Sep 04, 2017 at 02:54:50PM +0300, Yury Norov wrote:
> This is 4.13-based and next-20170901-based ilp32 patches.
> https://github.com/norov/linux/tree/ilp32-4.13
Thanks. I'll mirror it on kernel.org sometime this week after doing some
tests (I've been mostly away for the past two weeks).
On Wed, Nov 16, 2016 at 03:22:26PM +0400, Maxim Kuvyrkov wrote:
> Regarding ILP32 runtime, my opinion is that it is acceptable for ILP32
> to have extra failures compared to LP64, since these are not
> regressions, but, rather, failures of a new configuration.
I disagree with this. We definitely n
On Mon, Dec 05, 2016 at 06:16:09PM +0800, Zhangjian (Bamvor) wrote:
> Do you have suggestion of next move of upstreaming ILP32?
I mentioned the steps a few time before. I'm pasting them again here:
1. Complete the review of the Linux patches and ABI (no merge yet)
2. Review the corresponding glib
On Fri, Oct 21, 2016 at 11:33:08PM +0300, Yury Norov wrote:
> As we support more than one compat formats, it looks more reasonable
> to not use fs/compat_binfmt.c. Custom binfmt_elf32.c allows to move aarch32
> specific definitions there and make code more maintainable and readable.
Can you remind
On Fri, Oct 21, 2016 at 11:33:09PM +0300, Yury Norov wrote:
> binfmt_ilp32.c is needed to handle ILP32 binaries
>
> Signed-off-by: Yury Norov
> Signed-off-by: Bamvor Zhang Jian
> ---
> arch/arm64/include/asm/elf.h | 6 +++
> arch/arm64/kernel/Makefile | 1 +
> arch/arm64/kernel/binf
On Fri, Oct 21, 2016 at 11:33:13PM +0300, Yury Norov wrote:
> Signed-off-by: Yury Norov
Please add some description, even if it means copying the subject.
> ---
> arch/arm64/include/asm/signal32.h| 3 +
> arch/arm64/include/asm/signal32_common.h | 27 +++
> arch/arm64/kernel/Make
On Fri, Oct 21, 2016 at 11:33:15PM +0300, Yury Norov wrote:
> New aarch32 ptrace syscall handler is introduced to avoid run-time
> detection of the task type.
What's wrong with the run-time detection? If it's just to avoid a
negligible overhead, I would rather keep the code simpler by avoiding
dup
On Fri, Oct 21, 2016 at 11:33:10PM +0300, Yury Norov wrote:
> off_t is passed in register pair just like in aarch32.
> In this patch corresponding aarch32 handlers are shared to
> ilp32 code.
[...]
> +/*
> + * Note: off_4k (w5) is always in units of 4K. If we can't do the
> + * requested offset be
On Tue, Dec 06, 2016 at 11:55:08AM +0530, Yury Norov wrote:
> On Mon, Dec 05, 2016 at 04:34:23PM +0000, Catalin Marinas wrote:
> > On Fri, Oct 21, 2016 at 11:33:15PM +0300, Yury Norov wrote:
> > > New aarch32 ptrace syscall handler is introduced to avoid run-time
> > >
On Wed, Dec 07, 2016 at 09:40:13PM +0100, Arnd Bergmann wrote:
> On Wednesday, December 7, 2016 4:59:13 PM CET Catalin Marinas wrote:
> > On Tue, Dec 06, 2016 at 11:55:08AM +0530, Yury Norov wrote:
> > > On Mon, Dec 05, 2016 at 04:34:23PM +0000, Catalin Marinas wrote:
> >
On Wed, Apr 18, 2018 at 08:53:12PM +0200, Andrey Konovalov wrote:
> @@ -238,12 +239,15 @@ static inline void uaccess_enable_not_uao(void)
> /*
> * Sanitise a uaccess pointer such that it becomes NULL if above the
> * current addr_limit.
> + * Also untag user pointers that have the top byte tag
On Wed, Apr 18, 2018 at 08:53:13PM +0200, Andrey Konovalov wrote:
> diff --git a/mm/gup.c b/mm/gup.c
> index 76af4cfeaf68..fb375de7d40d 100644
> --- a/mm/gup.c
> +++ b/mm/gup.c
> @@ -386,6 +386,8 @@ struct page *follow_page_mask(struct vm_area_struct *vma,
> struct page *page;
> struct
On Wed, Apr 25, 2018 at 04:45:37PM +0200, Andrey Konovalov wrote:
> On Thu, Apr 19, 2018 at 11:33 AM, Kirill A. Shutemov
> wrote:
> > On Wed, Apr 18, 2018 at 08:53:09PM +0200, Andrey Konovalov wrote:
> >> arm64 has a feature called Top Byte Ignore, which allows to embed pointer
> >> tags into the
On Wed, May 02, 2018 at 07:25:17PM +0200, Andrey Konovalov wrote:
> On Wed, May 2, 2018 at 5:36 PM, Kirill A. Shutemov
> wrote:
> > On Wed, May 02, 2018 at 02:38:42PM +, Andrey Konovalov wrote:
> >> > Does having a tagged address here makes any difference? I couldn't hit a
> >> > failure with
Hi Andrey,
(sorry for the delay)
On Mon, Sep 17, 2018 at 07:01:00PM +0200, Andrey Konovalov wrote:
> I took another look at the changes this patchset does to the kernel
> and here are my thoughts:
>
> I see two ways how a (potentially tagged) user pointer gets into the kernel:
>
> 1. A pointer
On Tue, Oct 02, 2018 at 03:12:42PM +0200, Andrey Konovalov wrote:
> diff --git a/Documentation/arm64/tagged-pointers.txt
> b/Documentation/arm64/tagged-pointers.txt
> index a25a99e82bb1..ae877d185fdb 100644
> --- a/Documentation/arm64/tagged-pointers.txt
> +++ b/Documentation/arm64/tagged-pointers
On Wed, Oct 10, 2018 at 04:10:21PM +0200, Eugene Syromiatnikov wrote:
> I have some questions regarding AArch64 ILP32 implementation for which I
> failed to find an answer myself:
> * How ptrace() tracer is supposed to distinguish between ILP32 and LP64
>tracees? For MIPS N32 and x32 this is p
of hugepages supported by the arm64
> > >> kernel and the hugepage sizes enabled by each.
> > >>
> > >> Signed-off-by: Punit Agrawal
> > >> Cc: Catalin Marinas
> > >> Cc: Will Deacon
> > >> Cc: Jonathan Corbet
> > >
&
On Sat, Oct 13, 2018 at 04:07:31AM +0200, Eugene Syromiatnikov wrote:
> On Wed, Oct 10, 2018 at 03:39:07PM +0100, Szabolcs Nagy wrote:
> > On 10/10/18 15:10, Eugene Syromiatnikov wrote:
> > > * What's the reasoning behind capping syscall arguments to 32 bit? x32
> > >and MIPS N32 do not have s
On Sat, Oct 13, 2018 at 04:14:16AM +0200, Eugene Syromiatnikov wrote:
> On Wed, Oct 10, 2018 at 04:36:56PM +0100, Catalin Marinas wrote:
> > On Wed, Oct 10, 2018 at 04:10:21PM +0200, Eugene Syromiatnikov wrote:
> > > I have some questions regarding AArch64 ILP32 implemen
On Sun, Oct 14, 2018 at 09:49:01PM +0200, Arnd Bergmann wrote:
> On Sat, Oct 13, 2018 at 9:36 PM Andy Lutomirski wrote:
> >
> > On Wed, May 16, 2018 at 1:19 AM Yury Norov
> > wrote:
> > >
> > > This series enables AARCH64 with ILP32 mode.
> > >
> > > As supporting work, it introduces ARCH_32BIT_
On Wed, Oct 10, 2018 at 04:09:25PM +0200, Andrey Konovalov wrote:
> On Wed, Oct 3, 2018 at 7:32 PM, Catalin Marinas
> wrote:
> > On Tue, Oct 02, 2018 at 03:12:42PM +0200, Andrey Konovalov wrote:
[...]
> > Also, how is user space supposed to know that it can now pass tagged
>
On Wed, Oct 17, 2018 at 01:25:42PM -0700, Evgenii Stepanov wrote:
> On Wed, Oct 17, 2018 at 7:20 AM, Andrey Konovalov
> wrote:
> > On Wed, Oct 17, 2018 at 4:06 PM, Vincenzo Frascino
> > wrote:
> >> I have been thinking a bit lately on how to address the problem of
> >> user tagged pointers passe
On Tue, Nov 06, 2018 at 06:30:23PM +0100, Andrey Konovalov wrote:
> --- a/arch/arm64/include/asm/memory.h
> +++ b/arch/arm64/include/asm/memory.h
> @@ -92,6 +92,15 @@
> #define KASAN_THREAD_SHIFT 0
> #endif
>
> +#ifdef CONFIG_KASAN_SW_TAGS
> +#define KASAN_TAG_SHIFTED(tag) ((uns
On Tue, Nov 06, 2018 at 06:30:27PM +0100, Andrey Konovalov wrote:
> diff --git a/arch/arm64/mm/fault.c b/arch/arm64/mm/fault.c
> index 7d9571f4ae3d..d9a84d6f3343 100644
> --- a/arch/arm64/mm/fault.c
> +++ b/arch/arm64/mm/fault.c
> @@ -32,6 +32,7 @@
> #include
> #include
> #include
> +#include
Harb Abdulhamid)
> >-- IORT moved to required from recommended (Hanjun Guo)
> >-- Clarify IORT description (Hanjun Guo)
> >
> > Signed-off-by: Al Stone
> > Cc: Catalin Marinas
> > Cc: Will Deacon
> > Cc: Jonathan Corbet
> > ---
> >
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