On Sun, Sep 10, 2023 at 04:28:57AM -0400, guo...@kernel.org wrote:
> From: Guo Ren
>
> Cache-block prefetch instructions are HINTs to the hardware to
> indicate that software intends to perform a particular type of
> memory access in the near future. Enable ARCH_HAS_PREFETCHW and
> improve the ar
On Sun, Sep 10, 2023 at 04:28:57AM -0400, guo...@kernel.org wrote:
> From: Guo Ren
>
> Cache-block prefetch instructions are HINTs to the hardware to
> indicate that software intends to perform a particular type of
> memory access in the near future. Enable ARCH_HAS_PREFETCHW and
> improve the ar
On Thu, Sep 14, 2023 at 04:25:53PM +0200, Andrew Jones wrote:
> On Sun, Sep 10, 2023 at 04:28:57AM -0400, guo...@kernel.org wrote:
> > From: Guo Ren
> >
> > Cache-block prefetch instructions are HINTs to the hardware to
> > indicate that software intends to p
On Fri, Sep 15, 2023 at 05:22:26AM -0300, Leonardo Bras wrote:
> On Thu, Sep 14, 2023 at 03:47:59PM +0200, Andrew Jones wrote:
> > On Sun, Sep 10, 2023 at 04:28:57AM -0400, guo...@kernel.org wrote:
> > > From: Guo Ren
...
> > > diff --git a/arch/riscv/include/asm/ins
On Fri, Sep 15, 2023 at 12:37:50PM +0100, Conor Dooley wrote:
> Yo,
>
> On Thu, Sep 14, 2023 at 04:47:18PM +0200, Andrew Jones wrote:
> > On Thu, Sep 14, 2023 at 04:25:53PM +0200, Andrew Jones wrote:
> > > On Sun, Sep 10, 2023 at 04:28:57AM -0400, guo...@kernel.org wrot
On Fri, Sep 15, 2023 at 12:26:20PM +0100, Conor Dooley wrote:
> On Fri, Sep 15, 2023 at 01:07:40PM +0200, Andrew Jones wrote:
> > On Fri, Sep 15, 2023 at 05:22:26AM -0300, Leonardo Bras wrote:
> > > On Thu, Sep 14, 2023 at 03:47:59PM +0200, Andrew Jones wrote:
> > > >
On Wed, Jan 15, 2025 at 10:40:23AM +0800, Yunhui Cui wrote:
> Expose Zicbom through hwprobe and also provide a key to extract its
> respective block size.
>
> Signed-off-by: Yunhui Cui
> ---
> Documentation/arch/riscv/hwprobe.rst | 6 ++
> arch/riscv/include/asm/hwprobe.h | 2 +-
> arc
On Mon, Jan 13, 2025 at 07:29:39PM +0800, yunhui cui wrote:
> Hi drew,
>
> On Mon, Jan 13, 2025 at 5:07 PM Andrew Jones wrote:
> >
> > On Mon, Jan 13, 2025 at 04:36:34PM +0800, Yunhui Cui wrote:
> > > Expose Zicbom through hwprobe and also provide a key to extract i
On Mon, Jan 13, 2025 at 07:49:39PM +0800, yunhui cui wrote:
> Hi drew,
>
> On Mon, Jan 13, 2025 at 5:18 PM Andrew Jones wrote:
> >
> > On Mon, Jan 13, 2025 at 04:36:35PM +0800, Yunhui Cui wrote:
> > > Add test for Zicbom and its block size into CBO tests, when
>
On Mon, Jan 13, 2025 at 04:36:33PM +0800, Yunhui Cui wrote:
> Enabling cbo.clean and cbo.flush in user mode makes it more
> convenient to manage the cache state and achieve better performance.
>
> Reviewed-by: Andrew Jones
> Signed-off-by: Yunhui Cui
> ---
> arch/riscv/ke
On Mon, Jan 13, 2025 at 04:36:34PM +0800, Yunhui Cui wrote:
> Expose Zicbom through hwprobe and also provide a key to extract its
> respective block size.
>
> Signed-off-by: Yunhui Cui
> ---
> Documentation/arch/riscv/hwprobe.rst | 6 ++
> arch/riscv/include/asm/hwprobe.h | 2 +-
> arc
On Mon, Jan 13, 2025 at 04:36:35PM +0800, Yunhui Cui wrote:
> Add test for Zicbom and its block size into CBO tests, when
> Zicbom is present, test that cbo.clean/flush may be issued and works.
> As the software can't verify the clean/flush functions, we just judged
> that cbo.clean/flush isn't exe
t; tests[TEST_NO_ZICBOZ].enabled = true;
> tests[TEST_NO_ZICBOM].enabled = true;
> + tests[TEST_NO_ZICBOINVAL].enabled = true;
> }
>
> rc = sched_getaffinity(0, sizeof(cpu_set_t), &cpus);
> @@ -206,7 +243,14 @@ int main(int argc, char **argv)
> tests[TEST_ZICBOZ].enabled = true;
> tests[TEST_NO_ZICBOZ].enabled = false;
> } else {
> - check_no_zicboz_cpus(&cpus);
> + check_no_zicbo_cpus(&cpus, RISCV_HWPROBE_EXT_ZICBOZ);
> + }
> +
> + if (pair.value & RISCV_HWPROBE_EXT_ZICBOM) {
> + tests[TEST_ZICBOM].enabled = true;
> + tests[TEST_NO_ZICBOM].enabled = false;
> + } else {
> + check_no_zicbo_cpus(&cpus, RISCV_HWPROBE_EXT_ZICBOM);
> }
>
> for (i = 0; i < ARRAY_SIZE(tests); ++i)
> --
> 2.39.2
>
Besides the nit,
Reviewed-by: Andrew Jones
On Tue, Jan 14, 2025 at 08:17:02PM +0800, yunhui cui wrote:
> Hi Samuel，
>
> On Tue, Jan 14, 2025 at 1:28 PM Samuel Holland
> wrote:
> >
> > Hi Yunhui,
> >
> > On 2025-01-13 8:19 PM, Yunhui Cui wrote:
> > > Expose Zicbom through hwprobe and also provide a key to extract its
> > > respective block
sm/hwprobe.h | 2 +-
> arch/riscv/include/uapi/asm/hwprobe.h | 2 ++
> arch/riscv/kernel/sys_hwprobe.c | 6 ++
> 4 files changed, 15 insertions(+), 1 deletion(-)
>
Reviewed-by: Andrew Jones
On Mon, Mar 10, 2025 at 04:12:10PM +0100, Clément Léger wrote:
> Add FWFT extension calls. This will be ratified in SBI V3.0 hence, it is
> provided as a separate commit that can be left out if needed.
>
> Signed-off-by: Clément Léger
> ---
> arch/riscv/kernel/sbi.c | 30
struct
> kvm_sbi_fwft_config),
> + GFP_KERNEL);
> + if (!fwft->configs)
> + return -ENOMEM;
> +
> + for (i = 0; i < ARRAY_SIZE(features); i++) {
> + feature = &features[i];
> + conf = &fwft->configs[i];
> + if (feature->supported)
> + conf->supported = feature->supported(vcpu);
> + else
> + conf->supported = true;
> +
> + conf->feature = feature;
> + }
> +
> + return 0;
> +}
> +
> +static void kvm_sbi_ext_fwft_deinit(struct kvm_vcpu *vcpu)
> +{
> + struct kvm_sbi_fwft *fwft = vcpu_to_fwft(vcpu);
> +
> + kfree(fwft->configs);
> +}
> +
> +static void kvm_sbi_ext_fwft_reset(struct kvm_vcpu *vcpu)
> +{
> + int i = 0;
no need for '= 0'
> + struct kvm_sbi_fwft *fwft = vcpu_to_fwft(vcpu);
> +
> + for (i = 0; i < ARRAY_SIZE(features); i++)
> + fwft->configs[i].flags = 0;
> +}
> +
> +const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_fwft = {
> + .extid_start = SBI_EXT_FWFT,
> + .extid_end = SBI_EXT_FWFT,
> + .handler = kvm_sbi_ext_fwft_handler,
> + .init = kvm_sbi_ext_fwft_init,
> + .deinit = kvm_sbi_ext_fwft_deinit,
> + .reset = kvm_sbi_ext_fwft_reset,
> +};
> --
> 2.47.2
>
Reviewed-by: Andrew Jones
unsigned long *value)
> +{
> + *value = (csr_read(CSR_HEDELEG) & MIS_DELEG) != 0;
> +
> + return SBI_SUCCESS;
> +}
> +
> static const struct kvm_sbi_fwft_feature features[] = {
> + {
> + .id = SBI_FWFT_MISALIGNED_EXC_DELEG,
> + .supported = kvm_sbi_fwft_misaligned_delegation_supported,
> + .set = kvm_sbi_fwft_set_misaligned_delegation,
> + .get = kvm_sbi_fwft_get_misaligned_delegation,
> + },
> };
>
> static struct kvm_sbi_fwft_config *
> --
> 2.47.2
>
Reviewed-by: Andrew Jones
access_speed, cpu)
> - != RISCV_HWPROBE_MISALIGNED_SCALAR_EMULATED)
> - return false;
> + if (!all_cpus_unaligned_scalar_access_emulated())
> + return false;
>
> unaligned_ctl = true;
> return true;
> --
> 2.47.2
>
Reviewed-by: Andrew Jones
*/
> + return misaligned_traps_delegated ||
> +all_cpus_unaligned_scalar_access_emulated();
> +}
> +EXPORT_SYMBOL_GPL(misaligned_traps_can_delegate);
> \ No newline at end of file
Check your editor settings.
> --
> 2.47.2
Reviewed-by: Andrew Jones
On Mon, Mar 10, 2025 at 04:12:21PM +0100, Clément Léger wrote:
> The FWFT SBI extension will need to dynamically allocate memory and do
> init time specific initialization. Add an init/deinit callbacks that
> allows to do so.
>
> Signed-off-by: Clément Léger
> ---
> arch/riscv/include/asm/kvm_vc
pu_sbi_sta_reset(struct kvm_vcpu *vcpu)
> {
> vcpu->arch.sta.shmem = INVALID_GPA;
> vcpu->arch.sta.last_steal = 0;
> @@ -156,6 +156,7 @@ const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_sta = {
> .extid_end = SBI_EXT_STA,
> .handler = kvm_sbi_ext_sta_handler,
> .probe = kvm_sbi_ext_sta_probe,
> + .reset = kvm_riscv_vcpu_sbi_sta_reset,
> };
>
> int kvm_riscv_vcpu_get_reg_sbi_sta(struct kvm_vcpu *vcpu,
> --
> 2.47.2
>
Reviewed-by: Andrew Jones
by: Samuel Holland
> Reviewed-by: Deepak Gupta
> ---
> arch/riscv/include/asm/sbi.h | 33 +
> 1 file changed, 33 insertions(+)
>
Reviewed-by: Andrew Jones
On Mon, Mar 10, 2025 at 04:12:09PM +0100, Clément Léger wrote:
> This SBI extensions enables supervisor mode to control feature that are
> under M-mode control (For instance, Svadu menvcfg ADUE bit, Ssdbltrp
> DTE, etc).
>
> Signed-off-by: Clément Léger
> ---
> arch/riscv/include/asm/sbi.h | 5
make sense though since this line in handle_scalar_misaligned_load()
"belongs" to check_unaligned_access_emulated() which is also under
CONFIG_RISCV_SCALAR_MISALIGNED. Anyway, all this unaligned configs need a
major cleanup.
Reviewed-by: Andrew Jones
Thanks,
drew
>
> --
> 2.47.2
>
aligned_access_emulated);
> + on_each_cpu(check_unaligned_access_emulated, NULL, 1);
>
> for_each_online_cpu(cpu)
> if (per_cpu(misaligned_access_speed, cpu)
> --
> 2.47.2
>
Reviewed-by: Andrew Jones
_access_emulated(NULL);
> + ret = cpu_online_unaligned_access_init(cpu);
> + if (ret)
> + return ret;
> +
> + if (per_cpu(misaligned_access_speed, cpu) ==
> RISCV_HWPROBE_MISALIGNED_SCALAR_EMULATED)
> + goto exit;
> +
> buf = alloc_pages(GFP_KERNEL, MISALIGNED_BUFFER_ORDER);
> if (!buf) {
> pr_warn("Allocation failure, not measuring misaligned
> performance\n");
> @@ -403,6 +410,8 @@ static int check_unaligned_access_all_cpus(void)
> {
> bool all_cpus_emulated, all_cpus_vec_unsupported;
>
> + unaligned_access_init();
> +
> all_cpus_emulated = check_unaligned_access_emulated_all_cpus();
> all_cpus_vec_unsupported =
> check_vector_unaligned_access_emulated_all_cpus();
>
> --
> 2.47.2
>
Reviewed-by: Andrew Jones
On Fri, Mar 14, 2025 at 12:33:55PM +0100, Clément Léger wrote:
>
>
> On 13/03/2025 13:39, Andrew Jones wrote:
> > On Mon, Mar 10, 2025 at 04:12:09PM +0100, Clément Léger wrote:
> >> This SBI extensions enables supervisor mode to control feature that are
> >> u
On Mon, Mar 17, 2025 at 06:06:23PM +0100, Clément Léger wrote:
> Add basic infrastructure to support the FWFT extension in KVM.
>
> Signed-off-by: Clément Léger
> Reviewed-by: Andrew Jones
> ---
> arch/riscv/include/asm/kvm_host.h | 4 +
> arch/riscv/inclu
On Mon, Mar 17, 2025 at 06:06:10PM +0100, Clément Léger wrote:
> Add FWFT extension calls. This will be ratified in SBI V3.0 hence, it is
> provided as a separate commit that can be left out if needed.
>
> Signed-off-by: Clément Léger
> ---
> arch/riscv/kernel/sbi.c | 30
.feature = feature,
> + .value = value,
> + .flags = flags,
> + .error = ATOMIC_INIT(0),
> + };
> +
> + if (feature & SBI_FWFT_GLOBAL_FEATURE_BIT)
> + return -EINVAL;
> +
> + on_each_cpu_mask(mask, cpu_sbi_fwft_set, &req, 1);
> +
> + return atomic_read(&req.error);
> +}
> +
> /**
> * sbi_set_timer() - Program the timer for next timer event.
> * @stime_value: The value after which next timer event should fire.
> --
> 2.47.2
>
Otherwise,
Reviewed-by: Andrew Jones
ERR_NOT_SUPPORTED:
> case SBI_ERR_FAILURE:
> default:
> --
> 2.47.2
>
I'm not a huge fan sbi_err_map_linux_errno() since the mappings seem a bit
arbitrary, but if we're going to do it, then these look pretty good to me.
Only other thought I had was E2BIG for bad-range, but nah...
Reviewed-by: Andrew Jones
Thanks,
drew
idx < 0 || idx >= ARRAY_SIZE(scontext->ext_status))
> + continue;
> +
> + if (scontext->ext_status[idx] ==
> KVM_RISCV_SBI_EXT_STATUS_UNAVAILABLE ||
> + !ext->deinit)
> + continue;
> +
> + ext->deinit(vcpu);
> }
> }
> --
> 2.47.2
>
Reviewed-by: Andrew Jones
On Mon, Mar 24, 2025 at 09:29:33AM +0100, Clément Léger wrote:
>
>
> On 22/03/2025 13:06, Andrew Jones wrote:
> > On Mon, Mar 17, 2025 at 06:06:08PM +0100, Clément Léger wrote:
> >> A few new errors have been added with SBI V3.0, maps them as close as
>
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