On 14/03/2025 22:39, Deepak Gupta wrote:
Adding documentation on landing pad aka indirect branch tracking on riscv
and kernel interfaces exposed so that user tasks can enable it.
Reviewed-by: Zong Li
Signed-off-by: Deepak Gupta
---
Documentation/arch/riscv/index.rst | 1 +
Documentati
On 14/03/2025 22:39, Deepak Gupta wrote:
Adding documentation on shadow stack for user mode on riscv and kernel
interfaces exposed so that user tasks can enable it.
Reviewed-by: Zong Li
Signed-off-by: Deepak Gupta
---
Documentation/arch/riscv/index.rst | 1 +
Documentation/arch/riscv/
csrw CSR_SSP, s3),
+ 0,
+ RISCV_ISA_EXT_ZICFISS,
+ CONFIG_RISCV_USER_CFI)
+
1:
#ifdef CONFIG_RISCV_ISA_V_PREEMPTIVE
move a0, sp
Apart from the nits above, you can add:
Re
= PAGE_COPY,
+ [VM_WRITE] = PAGE_SHADOWSTACK,
[VM_WRITE | VM_READ]= PAGE_COPY,
[VM_EXEC] = PAGE_EXEC,
[VM_EXEC | VM_READ] = PAGE_READ_EXEC,
Reviewed-by: Alexandre Ghiti
On 14/03/2025 22:39, Deepak Gupta wrote:
Userspace specifies CLONE_VM to share address space and spawn new thread.
`clone` allow userspace to specify a new stack for new thread. However
there is no way to specify new shadow stack base address without changing
API. This patch allocates a new sha
On 14/03/2025 22:39, Deepak Gupta wrote:
From: Jim Shu
user mode tasks compiled with zicfilp may call indirectly into vdso (like
hwprobe indirect calls). Add landing pad compile support in vdso. vdso
with landing pad in it will be nop for tasks which have not enabled
landing pad.
This patch a
VM_SHADOW_STACK VM_HIGH_ARCH_5
+#endif
+
#ifndef VM_SHADOW_STACK
# define VM_SHADOW_STACK VM_NONE
#endif
Reviewed-by: Alexandre Ghiti
Thanks,
Alex
CV_ISA_EXT_ZICSR),
With the above comment fixed, you can add:
Reviewed-by: Alexandre Ghiti
Thanks,
Alex
On 14/03/2025 22:39, Deepak Gupta wrote:
Three architectures (x86, aarch64, riscv) have support for indirect branch
tracking feature in a very similar fashion. On a very high level, indirect
branch tracking is a CPU feature where CPU tracks branches which uses
memory operand to perform control tr
"Oops - store (or AMO) address
misaligned");
}
+ if (enable_irqs)
+ local_irq_disable();
+
irqentry_exit(regs, state);
}
Reviewed-by: Alexandre Ghiti
Thanks,
Alex
, controls whether unaligned
+traps are caught and emulated (instead of failing).
=
0 Do not emulate unaligned accesses.
Reviewed-by: Alexandre Ghiti
Thanks,
Alex
Hi Clément,
On 14/04/2025 14:34, Clément Léger wrote:
misaligned accesses traps are not nmi and should be treated as normal
one using irqentry_enter()/exit().
All the traps that come from kernel mode are treated as nmi as it was
suggested by Peter here:
https://lore.kernel.org/linux-riscv/
); \
+ __ret = get_user(insn, (type __user *) insn_addr); \
} else {\
insn = *(type *)insn_addr; \
__ret = 0; \
Reviewed-by: Alexandre Ghiti
Thanks,
Alex
}
+
DO_ERROR_INFO(do_trap_store_fault,
SIGSEGV, SEGV_ACCERR, "store (or AMO) access fault");
DO_ERROR_INFO(do_trap_ecall_s,
Reviewed-by: Alexandre Ghiti
Thanks,
Alex
ser_mode(regs)) {
+ local_irq_disable();
irqentry_exit_to_user_mode(regs);
- else
+ } else {
irqentry_nmi_exit(regs, state);
+ }
}
asmlinkage __visible __trap_section void do_trap_load_misaligned(struct pt_regs *regs)
Reviewed-by: Alexandre Ghiti
Thanks,
Alex
On Tue, Feb 25, 2025 at 2:27 PM yunhui cui wrote:
>
> Hi Alex,
>
> On Tue, Feb 25, 2025 at 9:21 PM Alexandre Ghiti
> wrote:
> >
> > Hi Yunhui,
> >
> > On Wed, Jan 15, 2025 at 3:40 AM Yunhui Cui wrote:
> > >
> > > v1/v2:
> > >
Hi Yunhui,
On Wed, Jan 15, 2025 at 3:40 AM Yunhui Cui wrote:
>
> v1/v2:
> There is only the first patch: RISC-V: Enable cbo.clean/flush in usermode,
> which mainly removes the enabling of cbo.inval in user mode.
>
> v3:
> Add the functionality of Expose Zicbom and selftests for Zicbom.
>
> v4:
>
Hi Clément,
On 22/04/2025 18:23, Clément Léger wrote:
This selftest tests (almost) all the currently emulated instruction
(except for the RV32 compressed ones which are left as a future
exercise for a RV32 user). For the FPU instructions, all the FPU
registers are tested.
Signed-off-by: Clément
Hi Radim,
On 06/05/2025 12:10, Radim Krčmář wrote:
[Ah, I missed v13 and v14, feel free to Cc me on next versions.]
2025-05-02T16:30:36-07:00, Deepak Gupta :
diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S
@@ -91,6 +91,32 @@
+.macro save_userssp tmp, status
+ ALTERNATI
Hi Deepak,
On 03/05/2025 01:30, Deepak Gupta wrote:
Kernel will have to perform shadow stack operations on user shadow stack.
Like during signal delivery and sigreturn, shadow stack token must be
created and validated respectively. Thus shadow stack access for kernel
must be enabled.
In future
On 6/4/25 21:32, Charlie Jenkins wrote:
On Wed, Jun 04, 2025 at 11:02:35AM -0700, Palmer Dabbelt wrote:
On Fri, 23 May 2025 03:19:17 PDT (-0700), cle...@rivosinc.com wrote:
The SBI Firmware Feature extension allows the S-mode to request some
specific features (either hardware or software) to be
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