Re: [PATCH v1] docs: reminder to not expose potentially private email addresses

Em Wed, 13 Nov 2024 11:59:39 +0100 Simona Vetter escreveu: > On Wed, 13 Nov 2024 at 11:55, Thorsten Leemhuis wrote: > > > > On 13.11.24 11:26, Laurent Pinchart wrote: > > > On Wed, Nov 13, 2024 at 09:35:03AM +0100, Thorsten Leemhuis wrote: > > >> Remind developers to not expose private email

Re: [PATCH v3] tpm: Opt-in in disable PCR integrity protection

On Wed, 2024-11-13 at 07:56 +0200, Jarkko Sakkinen wrote: > On Wed Nov 13, 2024 at 6:34 AM EET, Mimi Zohar wrote: > > The module_param variable documentation needs to be updated to reflect the > > actual module_param variable 'disable_pcr_integrity'. > > > > Otherwise, > > Tested-by: Mimi Zohar >

Re: [PATCH v1] docs: reminder to not expose potentially private email addresses

Em Wed, 13 Nov 2024 13:36:50 +0200 Laurent Pinchart escreveu: > On Wed, Nov 13, 2024 at 11:59:39AM +0100, Simona Vetter wrote: > > On Wed, 13 Nov 2024 at 11:55, Thorsten Leemhuis > > wrote: > > > > > > On 13.11.24 11:26, Laurent Pinchart wrote: > > > > On Wed, Nov 13, 2024 at 09:35:03AM +01

[PATCH net-next 2/4] netconsole: Add option to auto-populate CPU number in userdata

Add a new option to the netconsole subsystem to automatically populate the CPU number that is sending the log message in the userdata field. When enabled, this feature will append a "cpu=" entry to the userdata string, allowing the receiver to demultiplex and differentiate between messages sent fr

[PATCH net-next 3/4] netconsole: docs: Add documentation for CPU number auto-population

Update the netconsole documentation to explain the new feature that allows automatic population of the CPU number in the userdata field. The key changes include introducing a new section titled "CPU number auto population in userdata", explaining how to enable the CPU number auto-population featur

Re: [PATCH v8 24/29] riscv: enable kernel access to shadow stack memory via FWFT sbi call

Hi Deepak On Tue, Nov 12, 2024 at 5:08 AM Deepak Gupta wrote: > > Kernel will have to perform shadow stack operations on user shadow stack. > Like during signal delivery and sigreturn, shadow stack token must be > created and validated respectively. Thus shadow stack access for kernel > must be e

Re: [PATCH 2/3] KVM: x86: Add support for VMware guest specific hypercalls

On Wed, Nov 13, 2024 at 2:31 AM Paolo Bonzini wrote: > > > > Il mar 12 nov 2024, 21:44 Doug Covelli ha scritto: >> >> > Split irqchip should be the best tradeoff. Without it, moves from cr8 >> > stay in the kernel, but moves to cr8 always go to userspace with a >> > KVM_EXIT_SET_TPR exit. You als

Re: [RESEND PATCH V6 1/3] Documentation: remoteproc: update introduction section

On Tue, Nov 05, 2024 at 09:10:14PM -0800, anish kumar wrote: > Update the intrduction section to add key components > provided by remote processor framework. > > Signed-off-by: anish kumar > --- > Documentation/staging/remoteproc.rst | 17 + > 1 file changed, 17 insertions(+) >

Re: [RESEND PATCH V6 2/3] Documentation: remoteproc: add overview section

On Tue, Nov 05, 2024 at 09:10:15PM -0800, anish kumar wrote: > Added overview section which details > how the remote processor framework works and > how it handles crashes. > > Signed-off-by: anish kumar > --- > Documentation/staging/remoteproc.rst | 43 > 1 file cha

Re: [PATCH v1] docs: reminder to not expose potentially private email addresses

On 13.11.24 11:26, Laurent Pinchart wrote: > On Wed, Nov 13, 2024 at 09:35:03AM +0100, Thorsten Leemhuis wrote: >> Remind developers to not expose private email addresses, as some people >> become upset if their addresses end up in the lore archives or the Linux >> git tree. >> >> While at it, expl

Re: [PATCH v1] docs: reminder to not expose potentially private email addresses

On Wed, 13 Nov 2024 at 11:55, Thorsten Leemhuis wrote: > > On 13.11.24 11:26, Laurent Pinchart wrote: > > On Wed, Nov 13, 2024 at 09:35:03AM +0100, Thorsten Leemhuis wrote: > >> Remind developers to not expose private email addresses, as some people > >> become upset if their addresses end up in t

Re: [PATCH v1] docs: reminder to not expose potentially private email addresses

Hi Thorsten, On Wed, Nov 13, 2024 at 09:35:03AM +0100, Thorsten Leemhuis wrote: > Remind developers to not expose private email addresses, as some people > become upset if their addresses end up in the lore archives or the Linux > git tree. > > While at it, explicitly mention the dangers of our b

[PATCH v1] docs: reminder to not expose potentially private email addresses

Remind developers to not expose private email addresses, as some people become upset if their addresses end up in the lore archives or the Linux git tree. While at it, explicitly mention the dangers of our bugzilla instance here, as it makes it easy to forget that email addresses visible there are

Re: [PATCH v1] docs: reminder to not expose potentially private email addresses

On Wed, Nov 13, 2024 at 11:59:39AM +0100, Simona Vetter wrote: > On Wed, 13 Nov 2024 at 11:55, Thorsten Leemhuis wrote: > > > > On 13.11.24 11:26, Laurent Pinchart wrote: > > > On Wed, Nov 13, 2024 at 09:35:03AM +0100, Thorsten Leemhuis wrote: > > >> Remind developers to not expose private email a

Re: [PATCH 2/3] KVM: x86: Add support for VMware guest specific hypercalls

On 11/13/24 17:24, Doug Covelli wrote: No worries, you're not hijacking :) The only reason is that it would be more code for a seldom used feature and anyway with worse performance. (To be clear, CR8 based accesses are allowed, but stores cause an exit in order to check the new TPR against IRR. T

[PATCH net-next 1/4] netconsole: Ensure dynamic_netconsole_mutex is held during userdata update

Add a lock assertion to verify that dynamic_netconsole_mutex is held when updating the userdata fields in the netconsole driver. This change prevents calling update_userdata() without holding the lock, ensuring data consistency and integrity. The update_userdata() function is invoked only when th

Re: [PATCH v1] docs: reminder to not expose potentially private email addresses

On 13.11.24 12:40, Mauro Carvalho Chehab wrote: > Em Wed, 13 Nov 2024 11:59:39 +0100 > Simona Vetter escreveu: >> On Wed, 13 Nov 2024 at 11:55, Thorsten Leemhuis wrote: >>> On 13.11.24 11:26, Laurent Pinchart wrote: > +Note, remember to respect other people's privacy when adding these tags:

Re: [PATCH v1] docs: reminder to not expose potentially private email addresses

On Wed, Nov 13, 2024 at 2:20 PM Mauro Carvalho Chehab wrote: > Em Wed, 13 Nov 2024 13:36:50 +0200 > Laurent Pinchart escreveu: > > On Wed, Nov 13, 2024 at 11:59:39AM +0100, Simona Vetter wrote: > > > On Wed, 13 Nov 2024 at 11:55, Thorsten Leemhuis > > > wrote: > > > > On 13.11.24 11:26, Laurent

[PATCH net-next 0/4] netconsole: Add support for CPU population

The current implementation of netconsole sends all log messages in parallel, which can lead to an intermixed and interleaved output on the receiving side. This makes it challenging to demultiplex the messages and attribute them to their originating CPUs. As a result, users and developers often str

[PATCH net-next 4/4] netconsole: selftest: Validate CPU number auto-population in userdata

Expand the existing netconsole selftest to verify the functionality of the recently added CPU number auto-population feature in the netconsole userdata. The changes include enabling the "populate_cpu_nr" option on the netconsole target before sending the test data, and validating that the received

Re: [PATCH 2/3] KVM: x86: Add support for VMware guest specific hypercalls

On Wed, Nov 13, 2024, Paolo Bonzini wrote: > Il mar 12 nov 2024, 21:44 Doug Covelli ha > scritto: > > > > Split irqchip should be the best tradeoff. Without it, moves from cr8 > > > stay in the kernel, but moves to cr8 always go to userspace with a > > > KVM_EXIT_SET_TPR exit. You also won't be a

[PATCH v3] Documentation/CoC: spell out enforcement for unacceptable behaviors

The Code of Conduct committee's goal first and foremost is to bring about change to ensure our community continues to foster respectful discussions. In the interest of transparency, the CoC enforcement policy is formalized for unacceptable behaviors. Update the Code of Conduct Interpretation docu

Re: [PATCH v8 24/29] riscv: enable kernel access to shadow stack memory via FWFT sbi call

On Thu, Nov 14, 2024 at 09:20:14AM +0800, Nick Hu wrote: Hi Deepak On Thu, Nov 14, 2024 at 9:06 AM Deepak Gupta wrote: On Thu, Nov 14, 2024 at 12:13:38AM +0800, Nick Hu wrote: >Hi Deepak > >On Tue, Nov 12, 2024 at 5:08 AM Deepak Gupta wrote: >> >> Kernel will have to perform shadow stack ope

[PATCH v11 01/14] dt-bindings: riscv: Add xtheadvector ISA extension description

The xtheadvector ISA extension is described on the T-Head extension spec Github page [1] at commit 95358cb2cca9. Link: https://github.com/T-head-Semi/thead-extension-spec/blob/95358cb2cca9489361c61d335e03d3134b14133f/xtheadvector.adoc [1] Signed-off-by: Charlie Jenkins Reviewed-by: Conor Doole

[PATCH v11 02/14] dt-bindings: cpus: add a thead vlen register length property

Add a property analogous to the vlenb CSR so that software can detect the vector length of each CPU prior to it being brought online. Currently software has to assume that the vector length read from the boot CPU applies to all possible CPUs. On T-Head CPUs implementing pre-ratification vector, rea

[PATCH v11 05/14] riscv: vector: Use vlenb from DT for thead

If thead,vlenb is provided in the device tree, prefer that over reading the vlenb csr. Signed-off-by: Charlie Jenkins Acked-by: Conor Dooley --- arch/riscv/Kconfig.vendor| 13 +++ arch/riscv/include/asm/cpufeature.h | 2 + arch/riscv/include/asm/vendor_

[PATCH v11 04/14] riscv: Add thead and xtheadvector as a vendor extension

Add support to the kernel for THead vendor extensions with the target of the new extension xtheadvector. Signed-off-by: Charlie Jenkins Reviewed-by: Conor Dooley --- arch/riscv/Kconfig.vendor| 13 + arch/riscv/include/asm/vendor_extensions/thead.h | 16 ++

[PATCH v11 06/14] RISC-V: define the elements of the VCSR vector CSR

From: Heiko Stuebner The VCSR CSR contains two elements VXRM[2:1] and VXSAT[0]. Define constants for those to access the elements in a readable way. Acked-by: Guo Ren Reviewed-by: Conor Dooley Signed-off-by: Heiko Stuebner Signed-off-by: Charlie Jenkins --- arch/riscv/include/asm/csr.h | 4

[PATCH v11 07/14] riscv: csr: Add CSR encodings for CSR_VXRM/CSR_VXSAT

The VXRM vector csr for xtheadvector has an encoding of 0xa and VXSAT has an encoding of 0x9. Co-developed-by: Heiko Stuebner Signed-off-by: Heiko Stuebner Signed-off-by: Charlie Jenkins --- arch/riscv/include/asm/csr.h | 11 --- 1 file changed, 8 insertions(+), 3 deletions(-) diff --

[PATCH v11 03/14] riscv: dts: allwinner: Add xtheadvector to the D1/D1s devicetree

The D1/D1s SoCs support xtheadvector so it can be included in the devicetree. Also include vlenb for the cpu. Signed-off-by: Charlie Jenkins Reviewed-by: Conor Dooley --- arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/ris

[PATCH v11 08/14] riscv: Add xtheadvector instruction definitions

xtheadvector uses different encodings than standard vector for vsetvli and vector loads/stores. Write the instruction formats to be used in assembly code. Co-developed-by: Heiko Stuebner Signed-off-by: Heiko Stuebner Signed-off-by: Charlie Jenkins --- arch/riscv/include/asm/vendor_extensions/t

[PATCH v11 12/14] selftests: riscv: Fix vector tests

Overhaul the riscv vector tests to use kselftest_harness to help the test cases correctly report the results and decouple the individual test cases from each other. With this refactoring, only run the test cases if vector is reported and properly report the test case as skipped otherwise. The v_ini

[PATCH v11 13/14] selftests: riscv: Support xtheadvector in vector tests

Extend existing vector tests to be compatible with the xtheadvector instructions. Signed-off-by: Charlie Jenkins --- .../selftests/riscv/vector/v_exec_initval_nolibc.c | 23 -- tools/testing/selftests/riscv/vector/v_helpers.c | 17 - tools/testing/selftests/riscv/vector/v_helpers.h |

[PATCH v11 10/14] riscv: hwprobe: Add thead vendor extension probing

Add a new hwprobe key "RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0" which allows userspace to probe for the new RISCV_ISA_VENDOR_EXT_XTHEADVECTOR vendor extension. This new key will allow userspace code to probe for which thead vendor extensions are supported. This API is modeled to be consistent with RI

[PATCH v11 11/14] riscv: hwprobe: Document thead vendor extensions and xtheadvector extension

Document support for thead vendor extensions using the key RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0 and xtheadvector extension using the key RISCV_HWPROBE_VENDOR_EXT_XTHEADVECTOR. Signed-off-by: Charlie Jenkins Reviewed-by: Evan Green --- Documentation/arch/riscv/hwprobe.rst | 10 ++ 1 file

[PATCH v11 14/14] riscv: Add ghostwrite vulnerability

Follow the patterns of the other architectures that use GENERIC_CPU_VULNERABILITIES for riscv to introduce the ghostwrite vulnerability and mitigation. The mitigation is to disable all vector which is accomplished by clearing the bit from the cpufeature field. Ghostwrite only affects thead c9xx CP

Re: [PATCH v10 05/14] riscv: vector: Use vlenb from DT for thead

+0xc2/0xce > [ 978.789113] Code: a073 1007 006f 1a60 7057 0c30 57fd 17fe 77d7 0c30 (b057) > 5e0f > [ 978.789123] ---[ end trace ]--- > [ 978.789131] Kernel panic - not syncing: Fatal exception in interrupt > [ 978.937158] ---[ end Kernel panic - not syncing: Fat

[PATCH v11 09/14] riscv: vector: Support xtheadvector save/restore

Use alternatives to add support for xtheadvector vector save/restore routines. Signed-off-by: Charlie Jenkins Reviewed-by: Conor Dooley --- arch/riscv/include/asm/csr.h | 6 + arch/riscv/include/asm/switch_to.h | 2 +- arch/riscv/include/asm/vector.h| 222 +

Re: [PATCH v11 10/14] riscv: hwprobe: Add thead vendor extension probing

On Thu, Nov 14, 2024 at 11:26:47AM +0800, Yangyu Chen wrote: > > > On 11/14/24 11:02, Charlie Jenkins wrote: > > On Thu, Nov 14, 2024 at 10:44:37AM +0800, Yangyu Chen wrote: > > > > > > > > > On 11/14/24 10:21, Charlie Jenkins wrote: > > > > Add a new hwprobe key "RISCV_HWPROBE_KEY_VENDOR_EXT_T

Re: [PATCH v7 13/13] Documentation: userspace-api: iommufd: Update vIOMMU

On 2024/11/14 08:18, Nicolin Chen wrote: On Tue, Nov 12, 2024 at 09:15:02PM +0800, Yi Liu wrote: On 2024/11/6 04:04, Nicolin Chen wrote: +5. IOMMUFD_OBJ_VIOMMU can be only manually created via the IOMMU_VIOMMU_ALLOC + uAPI, provided a dev_id (for the device's physical IOMMU to back the vIOMMU

Re: [PATCH v7 13/13] Documentation: userspace-api: iommufd: Update vIOMMU

On Thu, Nov 14, 2024 at 11:13:00AM +0800, Yi Liu wrote: > On 2024/11/14 08:18, Nicolin Chen wrote: > > On Tue, Nov 12, 2024 at 09:15:02PM +0800, Yi Liu wrote: > > > On 2024/11/6 04:04, Nicolin Chen wrote: > > > > +5. IOMMUFD_OBJ_VIOMMU can be only manually created via the > > > > IOMMU_VIOMMU_ALLO

Re: [PATCH v7 13/13] Documentation: userspace-api: iommufd: Update vIOMMU

On Tue, Nov 12, 2024 at 09:15:02PM +0800, Yi Liu wrote: > On 2024/11/6 04:04, Nicolin Chen wrote: > > +5. IOMMUFD_OBJ_VIOMMU can be only manually created via the > > IOMMU_VIOMMU_ALLOC > > + uAPI, provided a dev_id (for the device's physical IOMMU to back the > > vIOMMU) > > + and an hwpt_id

[PATCH v11 00/14] riscv: Add support for xtheadvector

xtheadvector is a custom extension that is based upon riscv vector version 0.7.1 [1]. All of the vector routines have been modified to support this alternative vector version based upon whether xtheadvector was determined to be supported at boot. vlenb is not supported on the existing xtheadvector

Re: [PATCH v11 10/14] riscv: hwprobe: Add thead vendor extension probing

On 11/14/24 10:21, Charlie Jenkins wrote: Add a new hwprobe key "RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0" which allows userspace to probe for the new RISCV_ISA_VENDOR_EXT_XTHEADVECTOR vendor extension. Hi Charlie, How about changing the name of the key from "RISCV_ISA_VENDOR_EXT_XTHEADVECTOR

Re: [PATCH v10 00/14] riscv: Add support for xtheadvector

On Mon, Sep 30, 2024 at 12:07:23AM +0800, Aoba K wrote: > > On 2024/9/12 13:55, Charlie Jenkins wrote: > > xtheadvector is a custom extension that is based upon riscv vector > > version 0.7.1 [1]. All of the vector routines have been modified to > > support this alternative vector version based up

Re: [PATCH v11 10/14] riscv: hwprobe: Add thead vendor extension probing

On Thu, Nov 14, 2024 at 10:44:37AM +0800, Yangyu Chen wrote: > > > On 11/14/24 10:21, Charlie Jenkins wrote: > > Add a new hwprobe key "RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0" which > > allows userspace to probe for the new RISCV_ISA_VENDOR_EXT_XTHEADVECTOR > > vendor extension. > > > > Hi Charli

Re: [PATCH v8 24/29] riscv: enable kernel access to shadow stack memory via FWFT sbi call

On Thu, Nov 14, 2024 at 12:13:38AM +0800, Nick Hu wrote: Hi Deepak On Tue, Nov 12, 2024 at 5:08 AM Deepak Gupta wrote: Kernel will have to perform shadow stack operations on user shadow stack. Like during signal delivery and sigreturn, shadow stack token must be created and validated respecti

Re: [PATCH v8 24/29] riscv: enable kernel access to shadow stack memory via FWFT sbi call

Hi Deepak On Thu, Nov 14, 2024 at 9:06 AM Deepak Gupta wrote: > > On Thu, Nov 14, 2024 at 12:13:38AM +0800, Nick Hu wrote: > >Hi Deepak > > > >On Tue, Nov 12, 2024 at 5:08 AM Deepak Gupta wrote: > >> > >> Kernel will have to perform shadow stack operations on user shadow stack. > >> Like during

Re: [PATCH v11 10/14] riscv: hwprobe: Add thead vendor extension probing

On 11/14/24 11:02, Charlie Jenkins wrote: On Thu, Nov 14, 2024 at 10:44:37AM +0800, Yangyu Chen wrote: On 11/14/24 10:21, Charlie Jenkins wrote: Add a new hwprobe key "RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0" which allows userspace to probe for the new RISCV_ISA_VENDOR_EXT_XTHEADVECTOR vendor

Re: [PATCH v11 10/14] riscv: hwprobe: Add thead vendor extension probing

On 11/14/24 12:46, Charlie Jenkins wrote: On Thu, Nov 14, 2024 at 11:26:47AM +0800, Yangyu Chen wrote: On 11/14/24 11:02, Charlie Jenkins wrote: On Thu, Nov 14, 2024 at 10:44:37AM +0800, Yangyu Chen wrote: On 11/14/24 10:21, Charlie Jenkins wrote: Add a new hwprobe key "RISCV_HWPROBE_K

Re: [PATCH v11 10/14] riscv: hwprobe: Add thead vendor extension probing

On Thu, Nov 14, 2024 at 02:54:17PM +0800, Yangyu Chen wrote: > > > On 11/14/24 12:46, Charlie Jenkins wrote: > > On Thu, Nov 14, 2024 at 11:26:47AM +0800, Yangyu Chen wrote: > > > > > > > > > On 11/14/24 11:02, Charlie Jenkins wrote: > > > > On Thu, Nov 14, 2024 at 10:44:37AM +0800, Yangyu Chen

Re: [PATCH v8 24/29] riscv: enable kernel access to shadow stack memory via FWFT sbi call

Hi Deepak On Thu, Nov 14, 2024 at 9:25 AM Deepak Gupta wrote: > > On Thu, Nov 14, 2024 at 09:20:14AM +0800, Nick Hu wrote: > >Hi Deepak > > > >On Thu, Nov 14, 2024 at 9:06 AM Deepak Gupta wrote: > >> > >> On Thu, Nov 14, 2024 at 12:13:38AM +0800, Nick Hu wrote: > >> >Hi Deepak > >> > > >> >On Tu