Re: [PATCH 00/33] riscv control-flow integrity for usermode

Hello: This series was applied to riscv/linux.git (for-next) by Palmer Dabbelt : On Tue, 01 Oct 2024 09:06:05 -0700 you wrote: > v5 for cpu assisted riscv user mode control flow integrity. > zicfiss and zicfilp [1] are ratified riscv CPU extensions. > > Changes in this version are > - rebased on

Re: [PATCH v10 07/14] riscv: csr: Add CSR encodings for CSR_VXRM/CSR_VXSAT

Hi Charlie, Charlie Jenkins 於 2024年9月12日 週四 下午1:57寫道： > > The VXRM vector csr for xtheadvector has an encoding of 0xa and VXSAT > has an encoding of 0x9. > > Co-developed-by: Heiko Stuebner > Signed-off-by: Heiko Stuebner > Signed-off-by: Charlie Jenkins > --- > arch/riscv/include/asm/csr.h |

Re: [PATCH v10 06/14] RISC-V: define the elements of the VCSR vector CSR

Charlie Jenkins 於 2024年9月12日 週四 下午1:57寫道： > > From: Heiko Stuebner > > The VCSR CSR contains two elements VXRM[2:1] and VXSAT[0]. > > Define constants for those to access the elements in a readable way. > > Acked-by: Guo Ren > Reviewed-by: Conor Dooley > Signed-off-by: Heiko Stuebner > Signed-