On Fri, Mar 30, 2018 at 9:47 AM, Boris Brezillon
wrote:
> Add a driver for Cadence I3C GPIO expander.
>
> Signed-off-by: Boris Brezillon
This is pretty much OK, and I don't want to raise the bar
even higher for you to get this code into the kernel, so:
Acked-by: Linus Walleij
The following is
On 25/04/18 07:12, Sukadev Bhattiprolu wrote:
Yes. Like with PIDR, was trying to assign TIDR initially to all threads.
But since only a subset of threads need/use TIDR, we can assign the
value later (when set_thread_tidr() is called). So we should be able to
use task_pid_nr() then.
OK. Alastair
Hi,
On Wed, Apr 25, 2018 at 02:30:47PM +0530, Ganapatrao Kulkarni wrote:
> +
> +/* L3c and DMC has 16 and 8 channels per socket respectively.
> + * Each Channel supports UNCORE PMU device and consists of
> + * 4 independent programmable counters. Counters are 32 bit
> + * and does not support over
On Tue, Apr 10, 2018 at 10:30 PM, Bartosz Golaszewski wrote:
> Board files constitute a significant part of the users of the legacy
> GPIO framework. In many cases they only export a line and set its
> desired value. We could use GPIO hogs for that like we do for DT and
> ACPI but there's no supp
On Thu, Apr 12, 2018 at 10:00 PM, Christian Lamparter
wrote:
> The problem is that unlike native gpio-controllers, pinctrls need
> to have a "pin/gpio range" defined before any gpio-hogs can be added.
Indeed. But the primary use case (correct me if I am wrong Bartosz)
is to clean up old boardfil
Hi Kishon,
On 24/04/2018 12:24, Kishon Vijay Abraham I wrote:
> Hi,
>
> On Tuesday 24 April 2018 03:06 PM, Gustavo Pimentel wrote:
>> Hi Kishon,
>>
>> On 24/04/2018 08:07, Kishon Vijay Abraham I wrote:
>>> Hi,
>>>
>>> On Monday 23 April 2018 03:06 PM, Gustavo Pimentel wrote:
Hi Kishon,
Hi Kishon,
On 24/04/2018 12:43, Kishon Vijay Abraham I wrote:
> Hi,
>
> On Tuesday 24 April 2018 04:27 PM, Gustavo Pimentel wrote:
>> Hi Kishon,
>>
>> On 24/04/2018 08:19, Kishon Vijay Abraham I wrote:
>>> Hi,
>>>
>>> On Tuesday 17 April 2018 11:08 PM, Gustavo Pimentel wrote:
Hi Kishon,
On Wed, Apr 18, 2018 at 08:53:12PM +0200, Andrey Konovalov wrote:
> @@ -238,12 +239,15 @@ static inline void uaccess_enable_not_uao(void)
> /*
> * Sanitise a uaccess pointer such that it becomes NULL if above the
> * current addr_limit.
> + * Also untag user pointers that have the top byte tag
2018-04-26 14:07 GMT+02:00 Linus Walleij :
> On Tue, Apr 10, 2018 at 10:30 PM, Bartosz Golaszewski wrote:
>
>> Board files constitute a significant part of the users of the legacy
>> GPIO framework. In many cases they only export a line and set its
>> desired value. We could use GPIO hogs for that
On Wed, Apr 18, 2018 at 08:53:13PM +0200, Andrey Konovalov wrote:
> diff --git a/mm/gup.c b/mm/gup.c
> index 76af4cfeaf68..fb375de7d40d 100644
> --- a/mm/gup.c
> +++ b/mm/gup.c
> @@ -386,6 +386,8 @@ struct page *follow_page_mask(struct vm_area_struct *vma,
> struct page *page;
> struct
On Wed, Apr 25, 2018 at 04:45:37PM +0200, Andrey Konovalov wrote:
> On Thu, Apr 19, 2018 at 11:33 AM, Kirill A. Shutemov
> wrote:
> > On Wed, Apr 18, 2018 at 08:53:09PM +0200, Andrey Konovalov wrote:
> >> arm64 has a feature called Top Byte Ignore, which allows to embed pointer
> >> tags into the
Hi,
Just a few typo corrections...
On 04/25/2018 02:00 AM, Ganapatrao Kulkarni wrote:
> Documentation for the UNCORE PMUs on Cavium's ThunderX2 SoC.
> The SoC has PMU support in its L3 cache controller (L3C) and in the
> DDR4 Memory Controller (DMC).
>
> Signed-off-by: Ganapatrao Kulkarni
> ---
Some lines used spaces instead of tabs at line start.
This can cause mangled lines in editors due to inconsistency.
Replace spaces for tabs where appropriate.
Signed-off-by: Thymo van Beers
Reviewed-by: Randy Dunlap
---
Changes in v3:
- Change indentation in intel_pstate to reduce overrunning
On Wed, 25 Apr 2018 14:30:47 +0530
Ganapatrao Kulkarni wrote:
> +static int thunderx2_uncore_event_init(struct perf_event *event)
...
> + /*
> + * SOC PMU counters are shared across all cores.
> + * Therefore, it does not support per-process mode.
> + * Also, it does not suppor
)
CRC and Math Functions chapter
Signed-off-by: Randy Dunlap
---
Documentation/core-api/kernel-api.rst | 60
1 file changed, 30 insertions(+), 30 deletions(-)
--- linux-next-20180426.orig/Documentation/core-api/kernel-api.rst
+++ linux-next-20180426/Documentation/core
From: Alan Tull
Add fpga_region_create/free API functions.
Change fpga_region_register to take FPGA region struct as the only
parameter. Change fpga_region_unregister to return void.
struct fpga_region *fpga_region_create(struct device *dev,
struct fpga_manager *mgr,
From: Alan Tull
Change fpga_mgr_register to not set or use drvdata. This supports
the case where a PCIe device has more than one manager.
Add fpga_mgr_create/free functions. Change fpga_mgr_register and
fpga_mgr_unregister functions to take the mgr struct as their only
parameter.
struct fpg
Hi Greg,
Here's Alan's reworked patchset changing the API
for creating and registering FPGA Managers, Bridges and
Regions following your suggestions on the API.
These go on top of Paolo and Alan's patches that you
queued up the other day.
Thanks,
Moritz
Alan Tull (4):
fpga: region: don't use
From: Alan Tull
Changes to fpga_region_register function to not set drvdata.
Setting drvdata is fine for DT based devices that will have one region
per platform device. However PCIe based devices may have multiple
FPGA regions under one PCIe device. Without these changes, the PCIe
solution has
From: Alan Tull
Change fpga_bridge_register to not set drvdata. This is to support
the case where a PCIe device can have more than one bridge.
Add API functions to create/free the fpga bridge struct. Change
fpga_bridge_register/unregister to take FPGA bridge struct as
the only parameter.
str
driver-api/device_connection.rst |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- linux-next-20180426.orig/Documentation/driver-api/device_connection.rst
+++ linux-next-20180426/Documentation/driver-api/device_connection.rst
@@ -40,4 +40,4 @@ API
---
.. kernel-doc:: drivers/bas
On Fri, Apr 27, 2018 at 2:25 AM, Randy Dunlap wrote:
> Hi,
>
> Just a few typo corrections...
>
> On 04/25/2018 02:00 AM, Ganapatrao Kulkarni wrote:
>> Documentation for the UNCORE PMUs on Cavium's ThunderX2 SoC.
>> The SoC has PMU support in its L3 cache controller (L3C) and in the
>> DDR4 Memory
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