Re: [PATCH linux v2 5/6] hwmon: occ: Add hwmon implementation for the P8 OCC

On 01/11/2017 10:10 AM, eajames@gmail.com wrote: From: "Edward A. James" Add code to tie the hwmon sysfs code and the POWER8 OCC code together, as well as probe the entire driver from the I2C bus. I2C is the communication method between the BMC and the P8 OCC. Signed-off-by: Edward A. Jame

Re: [PATCH linux v2 2/6] hwmon: occ: Add sysfs interface

On 01/11/2017 10:10 AM, eajames@gmail.com wrote: From: "Edward A. James" Add a generic mechanism to expose the sensors provided by the OCC in sysfs. Signed-off-by: Edward A. James Signed-off-by: Andrew Jeffery --- Documentation/hwmon/occ | 62 ++ drivers/hwmon/occ/Makefil

Re: [PATCH linux v2 5/6] hwmon: occ: Add hwmon implementation for the P8 OCC

On 01/11/2017 10:10 AM, eajames@gmail.com wrote: From: "Edward A. James" Add code to tie the hwmon sysfs code and the POWER8 OCC code together, as well as probe the entire driver from the I2C bus. I2C is the communication method between the BMC and the P8 OCC. Signed-off-by: Edward A. Jame

Re: [PATCH linux v2 0/6] drivers: hwmon: Add On-Chip Controller driver

On 01/11/2017 10:10 AM, eajames@gmail.com wrote: From: "Edward A. James" This patchset adds a hwmon driver to support the OCC (On-Chip Controller) on the IBM POWER8 and POWER9 processors, from a BMC (Baseboard Management Controller). The OCC is an embedded processor that provides real time

Re: [PATCH linux v1 2/2] drivers: hwmon: hwmon driver for ASPEED AST2400/2500 PWM and Fan tach controller

On 01/09/2017 01:59 PM, Jaghathiswari Rankappagounder Natarajan wrote: The ASPEED AST2400/2500 PWM controller supports 8 PWM output ports. The ASPEED AST2400/2500 Fan tach controller supports 16 tachometer inputs. PWM clock types M, N and 0 are three types just to have three independent PWM sourc

Re: [PATCH 11/37] PCI: dwc: Split pcie-designware.c into host and core files

Hi Joao, On Friday 13 January 2017 10:19 PM, Joao Pinto wrote: > Às 10:26 AM de 1/12/2017, Kishon Vijay Abraham I escreveu: >> Split pcie-designware.c into pcie-designware-host.c that contains >> the host specific parts of the driver and pcie-designware.c that >> contains the parts used by both ho

Re: [PATCH 12/37] PCI: dwc: Create a new config symbol to enable pci dwc host

Hi Joao, On Friday 13 January 2017 11:20 PM, Joao Pinto wrote: > Hi Kishon, > > Às 10:26 AM de 1/12/2017, Kishon Vijay Abraham I escreveu: >> Now that pci designware host has a separate file, create a new >> config symbol to select the host only driver. This is in preparation >> to enable endpoin

Re: [PATCH 09/37] PCI: dwc: designware: Parse *num-lanes* property in dw_pcie_setup_rc

Hi, On Friday 13 January 2017 10:43 PM, Joao Pinto wrote: > Hi, > > Às 10:25 AM de 1/12/2017, Kishon Vijay Abraham I escreveu: >> *num-lanes* dt property is parsed in dw_pcie_host_init. However >> *num-lanes* property is applicable to both root complex mode and >> endpoint mode. As a first step,

Re: [PATCH 16/37] PCI: endpoint: Introduce configfs entry for configuring EP functions

Hi Christoph, On Friday 13 January 2017 11:36 PM, Christoph Hellwig wrote: > Hi Kishon, > > a couple comments on the configfs layout based on my experiments with > your previous drop to implement a NVMe device using it. Thanks for trying it out! > > I don't think most of these configfs files sh

Re: [PATCH 36/37] ARM: DRA7: clockdomain: Change the CLKTRCTRL of CM_PCIE_CLKSTCTRL to SW_WKUP

Hi Tony, On Friday 13 January 2017 10:45 PM, Tony Lindgren wrote: > * Kishon Vijay Abraham I [170112 02:35]: >> The PCIe programming sequence in TRM suggests CLKSTCTRL of PCIe should >> be set to SW_WKUP. There are no issues when CLKSTCTRL is set to HW_AUTO >> in RC mode. However in EP mode, the