Hi Oliver,
Thanks for the review comments.
> On 03/03/2016 04:38 PM, Ramesh Shanmugasundaram wrote:
>
> > Changes since v1:
> > * Removed testmodes & debugfs code (suggested by Oliver H)
> > * Fixed tx path race issue by introducing lock (suggested by Marc K)
> > * Removed __maybe_un
On 03/07/2016 09:02 AM, Ramesh Shanmugasundaram wrote:
> Hi Oliver,
>
> Thanks for the review comments.
>
>> On 03/03/2016 04:38 PM, Ramesh Shanmugasundaram wrote:
>>
>>> Changes since v1:
>>> * Removed testmodes & debugfs code (suggested by Oliver H)
>>> * Fixed tx path race issue by int
In the chapter 'analogy with reader-writer locking', the sample
code uses spinlock_t in reader-writer case. Just correct it so
that we can read the document easily.
Signed-off-by: Yao Dongdong
---
Documentation/RCU/whatisRCU.txt | 22 +++---
1 file changed, 15 insertions(+), 7
Hi Marc,
> On 03/07/2016 09:02 AM, Ramesh Shanmugasundaram wrote:
> > Hi Oliver,
> >
> > Thanks for the review comments.
> >
> >> On 03/03/2016 04:38 PM, Ramesh Shanmugasundaram wrote:
> >>
> >>> Changes since v1:
> >>> * Removed testmodes & debugfs code (suggested by Oliver H)
> >>> * Fixed t
On vr, 2016-03-04 at 17:32 +0100, Arnd Bergmann wrote:
> A third patch moves the capidrv source from drivers/isdn/capi/
> into the i4l directory.
I see. Why exactly?
Thanks,
Paul Bolle
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On za, 2016-03-05 at 14:08 +0100, Tilman Schmidt wrote:
> As a consequence, owners of HiSAX type adapters are in fact stuck with
> the old hisax driver if they want to continue using i4l userspace
> tools.
Do you know whether or not mISDN tools offer functionality comparable to
i4l tools?
Paul B
On Mon, Mar 07, 2016 at 12:29:08AM +0100, Johannes Stezenbach wrote:
> On Sat, Mar 05, 2016 at 11:29:37PM -0300, Mauro Carvalho Chehab wrote:
> >
> > I converted one of the big tables to CSV. At least now it recognized
> > it as a table. Yet, the table was very badly formated:
> >
> > https:/
Hi Rob,
Thanks for the review comments.
> On Thu, Mar 03, 2016 at 03:38:35PM +, Ramesh Shanmugasundaram wrote:
> > This patch adds support for the CAN FD controller found in Renesas
> > R-Car SoCs. The controller operates in CAN FD mode by default.
> >
> > CAN FD mode supports both Classical
Em Mon, 7 Mar 2016 09:48:26 +0100
Johannes Stezenbach escreveu:
> On Mon, Mar 07, 2016 at 12:29:08AM +0100, Johannes Stezenbach wrote:
> > On Sat, Mar 05, 2016 at 11:29:37PM -0300, Mauro Carvalho Chehab wrote:
> > >
> > > I converted one of the big tables to CSV. At least now it recognized
> >
Em Mon, 7 Mar 2016 00:29:08 +0100
Johannes Stezenbach escreveu:
> On Sat, Mar 05, 2016 at 11:29:37PM -0300, Mauro Carvalho Chehab wrote:
> >
> > I converted one of the big tables to CSV. At least now it recognized
> > it as a table. Yet, the table was very badly formated:
> >
> > https://mc
Add documentation for the tpm_vtpm device driver that implements
support for providing TPM functionality to Linux containers.
Parts of this documentation were recycled from the Xen vTPM
device driver documentation.
Signed-off-by: Stefan Berger
CC: linux-ker...@vger.kernel.org
CC: linux-doc@vger.
Add the retrieval of TPM 1.2 durations and timeouts. Since this requires
the startup of the TPM, do this for TPM 1.2 and TPM 2.
Signed-off-by: Stefan Berger
CC: linux-ker...@vger.kernel.org
CC: linux-doc@vger.kernel.org
CC: linux-...@vger.kernel.org
---
drivers/char/tpm/tpm_vtpm.c | 94 +
This patch implements a driver for supporting multiple emulated TPMs in a
system.
The driver implements a device /dev/vtpmx that is used to created
a client device pair /dev/tpmX (e.g., /dev/tpm10) and a server side that
is accessed using a file descriptor returned by an ioctl.
The device /dev/tpm
James Johnston wrote:
> -If CONFIG_MODULE_SIG_FORCE is enabled or enforcemodulesig=1 is supplied on
> +If CONFIG_MODULE_SIG_FORCE is enabled or module.sig_enforce=1 is supplied
You're definitely right about the change from enforcemodulesig to sig_enforce,
but how does the "module." come about?
On 03/05/2016 09:07 PM, David Miller wrote:
From: Khalid Aziz
Date: Wed, 2 Mar 2016 13:39:37 -0700
In this
first implementation I am enabling ADI for hugepages only
since these pages are locked in memory and hence avoid the
issue of saving and restoring tags.
On 03/07/2016 07:07 AM, Khalid Aziz wrote:
On 03/05/2016 09:07 PM, David Miller wrote:
From: Khalid Aziz
Date: Wed, 2 Mar 2016 13:39:37 -0700
In this
first implementation I am enabling ADI for hugepages only
since these pages are locked in memory and hence avoid the
issue of
On Mon, Mar 7, 2016 at 7:30 AM, Rob Gardner wrote:
> On 03/07/2016 07:07 AM, Khalid Aziz wrote:
>>
>> On 03/05/2016 09:07 PM, David Miller wrote:
>>>
>>> From: Khalid Aziz
>>> Date: Wed, 2 Mar 2016 13:39:37 -0700
>>>
In this
first implementation I am enabling ADI for hugepages
On 03/07/2016 08:30 AM, Rob Gardner wrote:
On 03/07/2016 07:07 AM, Khalid Aziz wrote:
On 03/05/2016 09:07 PM, David Miller wrote:
From: Khalid Aziz
Date: Wed, 2 Mar 2016 13:39:37 -0700
In this
first implementation I am enabling ADI for hugepages only
since these pages are locked
On 03/07/2016 08:43 AM, Andy Lutomirski wrote:
On Mon, Mar 7, 2016 at 7:30 AM, Rob Gardner wrote:
On 03/07/2016 07:07 AM, Khalid Aziz wrote:
On 03/05/2016 09:07 PM, David Miller wrote:
From: Khalid Aziz
Date: Wed, 2 Mar 2016 13:39:37 -0700
In this
first implementation I am ena
On Sat, 5 Mar 2016, Rob Herring wrote:
> On Thu, Feb 25, 2016 at 05:25:07PM -0600, Alan Tull wrote:
> > Add bindings documentation for Altera SOCFPGA bridges:
> > * fpga2sdram
> > * fpga2hps
> > * hps2fpga
> > * lwhps2fpga
> >
> > Signed-off-by: Alan Tull
> > Signed-off-by: Matthew Gerlach
From: Khalid Aziz
Date: Mon, 7 Mar 2016 08:07:53 -0700
> I can remove CONFIG_SPARC_ADI. It does mean this code will be built
> into 32-bit kernels as well but it will be inactive code.
The code should be built only into obj-$(CONFIG_SPARC64) just like the
rest of the 64-bit specific code. I don
From: Khalid Aziz
Date: Mon, 7 Mar 2016 08:07:53 -0700
> PR_GET_SPARC_ADICAPS
Put this into a new ELF auxiliary vector entry via ARCH_DLINFO.
So now all that's left is supposedly the TAG stuff, please explain
that to me so I can direct you to the correct existing interface to
provide that as we
On 03/02/2016 12:39 PM, Khalid Aziz wrote:
> --- a/include/uapi/asm-generic/siginfo.h
> +++ b/include/uapi/asm-generic/siginfo.h
> @@ -206,7 +206,10 @@ typedef struct siginfo {
> #define SEGV_MAPERR (__SI_FAULT|1) /* address not mapped to object */
> #define SEGV_ACCERR (__SI_FAULT|2) /* inva
On 03/02/2016 12:39 PM, Khalid Aziz wrote:
> +long enable_sparc_adi(unsigned long addr, unsigned long len)
> +{
> + unsigned long end, pagemask;
> + int error;
> + struct vm_area_struct *vma, *vma2;
> + struct mm_struct *mm;
> +
> + if (!ADI_CAPABLE())
> + return -EI
Hi Wim,
On Sun, Mar 06, 2016 at 11:49:56AM +0100, Wim Van Sebroeck wrote:
> Hi Guenter,
>
> > The watchdog infrastructure is currently purely passive, meaning
> > it only passes information from user space to drivers and vice versa.
> >
[ ... ]
>
> Patches 1 till 7 of this series has been added
On 03/07/2016 08:06 AM, Khalid Aziz wrote:
> Top 4-bits of sparc64 virtual address are used for version tag only when
> a process has its PSTATE.mcde bit set and it is accessing a memory
> region that has ADI enabled on it (TTE.mcd set) and a version tag was
> set on the virtual address being acces
On 03/07/2016 09:45 AM, David Miller wrote:
From: Khalid Aziz
Date: Mon, 7 Mar 2016 08:07:53 -0700
I can remove CONFIG_SPARC_ADI. It does mean this code will be built
into 32-bit kernels as well but it will be inactive code.
The code should be built only into obj-$(CONFIG_SPARC64) just like
On Mon, Mar 7, 2016 at 9:46 AM, Dave Hansen wrote:
> On 03/07/2016 08:06 AM, Khalid Aziz wrote:
>> Top 4-bits of sparc64 virtual address are used for version tag only when
>> a process has its PSTATE.mcde bit set and it is accessing a memory
>> region that has ADI enabled on it (TTE.mcd set) and a
On 03/07/2016 09:56 AM, David Miller wrote:
From: Khalid Aziz
Date: Mon, 7 Mar 2016 08:07:53 -0700
PR_GET_SPARC_ADICAPS
Put this into a new ELF auxiliary vector entry via ARCH_DLINFO.
So now all that's left is supposedly the TAG stuff, please explain
that to me so I can direct you to the co
On Mon, Mar 7, 2016 at 10:04 AM, Khalid Aziz wrote:
> On 03/07/2016 09:56 AM, David Miller wrote:
>>
>> From: Khalid Aziz
>> Date: Mon, 7 Mar 2016 08:07:53 -0700
>>
>>> PR_GET_SPARC_ADICAPS
>>
>>
>> Put this into a new ELF auxiliary vector entry via ARCH_DLINFO.
>>
>> So now all that's left is su
On 03/07/2016 09:53 AM, Andy Lutomirski wrote:
> Also, what am I missing? Tying these tags to the physical page seems
> like a poor design to me. This seems really awkward to use.
Yeah, can you describe the structures that store these things? Surely
the hardware has some kind of lookup tables f
On 03/07/2016 10:04 AM, Khalid Aziz wrote:
On 03/07/2016 09:56 AM, David Miller wrote:
From: Khalid Aziz
Date: Mon, 7 Mar 2016 08:07:53 -0700
PR_GET_SPARC_ADICAPS
Put this into a new ELF auxiliary vector entry via ARCH_DLINFO.
So now all that's left is supposedly the TAG stuff, please expl
On 03/07/2016 10:35 AM, Dave Hansen wrote:
On 03/02/2016 12:39 PM, Khalid Aziz wrote:
+long enable_sparc_adi(unsigned long addr, unsigned long len)
+{
+ unsigned long end, pagemask;
+ int error;
+ struct vm_area_struct *vma, *vma2;
+ struct mm_struct *mm;
+
+ if (!A
On 03/07/2016 11:08 AM, Andy Lutomirski wrote:
On Mon, Mar 7, 2016 at 10:04 AM, Khalid Aziz wrote:
On 03/07/2016 09:56 AM, David Miller wrote:
From: Khalid Aziz
Date: Mon, 7 Mar 2016 08:07:53 -0700
PR_GET_SPARC_ADICAPS
Put this into a new ELF auxiliary vector entry via ARCH_DLINFO.
So
On 03/07/2016 11:09 AM, Rob Gardner wrote:
On 03/07/2016 10:04 AM, Khalid Aziz wrote:
On 03/07/2016 09:56 AM, David Miller wrote:
From: Khalid Aziz
Date: Mon, 7 Mar 2016 08:07:53 -0700
PR_GET_SPARC_ADICAPS
Put this into a new ELF auxiliary vector entry via ARCH_DLINFO.
So now all that's l
On 03/07/2016 11:12 AM, Dave Hansen wrote:
On 03/07/2016 09:53 AM, Andy Lutomirski wrote:
Also, what am I missing? Tying these tags to the physical page seems
like a poor design to me. This seems really awkward to use.
Yeah, can you describe the structures that store these things? Surely
th
On Mon, Mar 7, 2016 at 10:22 AM, Khalid Aziz wrote:
> On 03/07/2016 11:08 AM, Andy Lutomirski wrote:
>>
>> On Mon, Mar 7, 2016 at 10:04 AM, Khalid Aziz
>> wrote:
>>>
>>> On 03/07/2016 09:56 AM, David Miller wrote:
From: Khalid Aziz
Date: Mon, 7 Mar 2016 08:07:53 -0700
>>
Hi Guenter,
> Hi Wim,
>
> On Sun, Mar 06, 2016 at 11:49:56AM +0100, Wim Van Sebroeck wrote:
> > Hi Guenter,
> >
> > > The watchdog infrastructure is currently purely passive, meaning
> > > it only passes information from user space to drivers and vice versa.
> > >
> [ ... ]
> >
> > Patches 1 t
On Mon, Mar 7, 2016 at 10:39 AM, Khalid Aziz wrote:
> On 03/07/2016 11:12 AM, Dave Hansen wrote:
>>
>> On 03/07/2016 09:53 AM, Andy Lutomirski wrote:
>>>
>>> Also, what am I missing? Tying these tags to the physical page seems
>>> like a poor design to me. This seems really awkward to use.
>>
>>
From: Dave Hansen
Date: Mon, 7 Mar 2016 09:35:57 -0800
> On 03/02/2016 12:39 PM, Khalid Aziz wrote:
>> +long enable_sparc_adi(unsigned long addr, unsigned long len)
>> +{
>> +unsigned long end, pagemask;
>> +int error;
>> +struct vm_area_struct *vma, *vma2;
>> +struct mm_struct *m
From: Khalid Aziz
Date: Mon, 7 Mar 2016 11:04:38 -0700
> On 03/07/2016 09:56 AM, David Miller wrote:
>> From: Khalid Aziz
>> Date: Mon, 7 Mar 2016 08:07:53 -0700
>>
>>> PR_GET_SPARC_ADICAPS
>>
>> Put this into a new ELF auxiliary vector entry via ARCH_DLINFO.
>>
>> So now all that's left is supp
From: Khalid Aziz
Date: Mon, 7 Mar 2016 11:24:54 -0700
> Tags can be cleared by user by setting tag to 0. Tags are
> automatically cleared by the hardware when the mapping for a virtual
> address is removed from TSB (which is why swappable pages are a
> problem), so kernel does not have to do it
From: Andy Lutomirski
Date: Mon, 7 Mar 2016 10:49:57 -0800
> What data structure or structures changes when this stxa instruction happens?
An internal table, maintained by the CPU and/or hypervisor, and if in physical
addresses then in a region which is only accessible by the hypervisor.
The ta
From: Andy Lutomirski
Date: Mon, 7 Mar 2016 10:53:23 -0800
> x86 has an upcoming feature called protection keys. A page of virtual
> memory has a protection key, which is a number from 0 through 16. The
> master copy is in the PTE, i.e. page table entry, which is a
> software-managed data struc
From: Thor Thayer
Force L2 cache dependency instead of forcing selection of
L2 cache.
Signed-off-by: Thor Thayer
---
v2 No change
---
drivers/edac/Kconfig |5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
index 37755e6..6ca7
This version splits the larger patch in V1 into smaller,
patches.
[PATCHv2 01/11] EDAC: Altera L2 Kconfig change from select to
[PATCHv2 02/11] EDAC, altera: Move Device structs and defines to
[PATCHv2 03/11] EDAC, altera: Add register offset for ECC Enable
[PATCHv2 04/11] EDAC, altera: Add re
From: Thor Thayer
In preparation for the Arria10 peripheral ECCs, a register
offset from the ECC base was added to the private data
structure to index to the error clear register. Since
the Arria10 L2 cache ECC registers are not contiguous,
a status base address was added.
Signed-off-by: Thor Th
From: Thor Thayer
Add the device tree binding string needed to support the Altera L2
cache on the Arria10 chip.
Signed-off-by: Thor Thayer
Acked-by: Rob Herring
---
v2 Correct spelling of Arria10 in patch title.
---
.../bindings/arm/altera/socfpga-eccmgr.txt |3 ++-
1 file changed
From: Thor Thayer
Move the device structs and defines to altera_edac.h in preparation
for adding the Arria10 L2 cache ECC.
Signed-off-by: Thor Thayer
---
v2: Split original patch into smaller patches. Move private data
and defines into header file.
---
drivers/edac/altera_edac.c | 43 ---
From: Thor Thayer
In preparation for the Arria10 peripheral ECCs, a register
offset from the ECC base was added to the private data
structure to index into the ECC enable register.
Signed-off-by: Thor Thayer
---
v2: Split large patch into smaller patches. Add an ECC
control offset to suppor
From: Thor Thayer
In preparation for the Arria10 peripheral ECCs, the IRQ
status needs to be determined because the IRQs are shared.
The IRQ status register is read to determine if the IRQ
was for this ECC peripheral. Cyclone5 and Arria5 have
dedicated IRQs so the confirmation mechanism is not
re
From: Thor Thayer
In preparation for the Arria10 peripheral ECCs, irq_flags
was added to the private data structure because Arria10
uses shared IRQs while Cyclone5/Arria5 have exclusive IRQs.
Signed-off-by: Thor Thayer
---
v2: Split large patch into smaller patches. Add irq_flags
to the pri
From: Thor Thayer
Enable ECC for Arria10 L2 cache on machine startup. The ECC has to be
enabled before data is stored in memory otherwise the ECC will fail
on reads.
Use DT_MACHINE to select Arria10 L2 cache function.
Signed-off-by: Thor Thayer
---
v2: Split into 2 separate functions selected w
From: Thor Thayer
In preparation for the Arria10 peripheral ECCs, a register
offset from the ECC base was added to the private data
structure to index to the error injection register.
Signed-off-by: Thor Thayer
---
v2: Split large patch into smaller patches. Add an ECC
error inject offset t
On 03/07/2016 12:22 PM, David Miller wrote:
Khalid, maybe you should share notes with the folks working on x86
protection keys.
Good idea. Sparc ADI feature is indeed similar to x86 protection keys
sounds like.
Thanks,
Khalid
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On 03/07/2016 11:49 AM, Andy Lutomirski wrote:
On Mon, Mar 7, 2016 at 10:22 AM, Khalid Aziz wrote:
No, it changes the tag associated with the virtual address for the caller.
Physical page backing this virtual address is unaffected. Tag checking is
done for virtual addresses. The one restriction
On Mon, Mar 7, 2016 at 11:44 AM, Khalid Aziz wrote:
> On 03/07/2016 11:49 AM, Andy Lutomirski wrote:
>>
>> On Mon, Mar 7, 2016 at 10:22 AM, Khalid Aziz
>> wrote:
>>>
>>> No, it changes the tag associated with the virtual address for the
>>> caller.
>>> Physical page backing this virtual address i
From: Thor Thayer
Addition of the Arria10 L2 Cache ECC handling. Addition
of private data structure for Arria10 L2 cache ECC and
the initialization function for it.
Signed-off-by: Thor Thayer
---
v2: Split large patch into smaller patches. Addition of
Arria10 L2 cache dependency check and p
From: Thor Thayer
Add the device tree entries needed to support the Altera L2
cache EDAC on the Arria10 chip.
Signed-off-by: Thor Thayer
---
v2 Match register value (l2-ecc@ffd06010)
---
arch/arm/boot/dts/socfpga_arria10.dtsi | 14 ++
1 file changed, 14 insertions(+)
diff --git
On Mon, Mar 07, 2016 at 04:02:14PM +0800, Yao Dongdong wrote:
> In the chapter 'analogy with reader-writer locking', the sample
> code uses spinlock_t in reader-writer case. Just correct it so
> that we can read the document easily.
>
> Signed-off-by: Yao Dongdong
Good catch, queued for review.
On 03/07/2016 12:54 PM, Andy Lutomirski wrote:
On Mon, Mar 7, 2016 at 11:44 AM, Khalid Aziz wrote:
Consider this scenario:
1. Process A creates a shm and attaches to it.
2. Process A fills shm with data it wants to share with only known
processes. It enables ADI and sets tags on the shm.
3. H
From: Khalid Aziz
Date: Mon, 7 Mar 2016 13:41:39 -0700
> Shared data may not always be backed by a file. My understanding is
> one of the use cases is for in-memory databases. This shared space
> could also be used to hand off transactions in flight to other
> processes. These transactions in fli
On Mon, Mar 7, 2016 at 12:58 PM, David Miller wrote:
> From: Khalid Aziz
> Date: Mon, 7 Mar 2016 13:41:39 -0700
>
>> Shared data may not always be backed by a file. My understanding is
>> one of the use cases is for in-memory databases. This shared space
>> could also be used to hand off transact
On 03/07/2016 10:46 AM, Dave Hansen wrote:
On 03/07/2016 08:06 AM, Khalid Aziz wrote:
Top 4-bits of sparc64 virtual address are used for version tag only when
a process has its PSTATE.mcde bit set and it is accessing a memory
region that has ADI enabled on it (TTE.mcd set) and a version tag was
On 03/07/2016 01:58 PM, David Miller wrote:
From: Khalid Aziz
Date: Mon, 7 Mar 2016 13:41:39 -0700
Shared data may not always be backed by a file. My understanding is
one of the use cases is for in-memory databases. This shared space
could also be used to hand off transactions in flight to oth
On 03/07/2016 12:09 PM, David Miller wrote:
From: Khalid Aziz
Date: Mon, 7 Mar 2016 11:04:38 -0700
On 03/07/2016 09:56 AM, David Miller wrote:
From: Khalid Aziz
Date: Mon, 7 Mar 2016 08:07:53 -0700
PR_GET_SPARC_ADICAPS
Put this into a new ELF auxiliary vector entry via ARCH_DLINFO.
So n
On 03/07/2016 12:16 PM, David Miller wrote:
From: Khalid Aziz
Date: Mon, 7 Mar 2016 11:24:54 -0700
Tags can be cleared by user by setting tag to 0. Tags are
automatically cleared by the hardware when the mapping for a virtual
address is removed from TSB (which is why swappable pages are a
prob
From: Khalid Aziz
Date: Mon, 7 Mar 2016 14:27:09 -0700
> I agree with your point of view. PSTATE.mcde and TTE.mcd are set in
> response to request from userspace. If userspace asked for them to be
> set, they already know but it was the database guys that asked for
> these two functions and they
From: Khalid Aziz
Date: Mon, 7 Mar 2016 14:33:56 -0700
> On 03/07/2016 12:16 PM, David Miller wrote:
>> From: Khalid Aziz
>> Date: Mon, 7 Mar 2016 11:24:54 -0700
>>
>>> Tags can be cleared by user by setting tag to 0. Tags are
>>> automatically cleared by the hardware when the mapping for a virt
On 03/07/2016 02:34 PM, David Miller wrote:
From: Khalid Aziz
Date: Mon, 7 Mar 2016 14:27:09 -0700
I agree with your point of view. PSTATE.mcde and TTE.mcd are set in
response to request from userspace. If userspace asked for them to be
set, they already know but it was the database guys that
On 03/07/2016 11:46 AM, Khalid Aziz wrote:
> On 03/07/2016 12:22 PM, David Miller wrote:
>> Khalid, maybe you should share notes with the folks working on x86
>> protection keys.
>
> Good idea. Sparc ADI feature is indeed similar to x86 protection keys
> sounds like.
There are definitely some sim
On 03/07/2016 01:33 PM, Khalid Aziz wrote:
That is a possibility but limited in scope. An address range covered
by a single TTE can have large number of tags. Version tags are set on
cacheline. In extreme case, one could set a tag for each set of
64-bytes in a page. Also tags are set complete
On 03/07/2016 01:38 PM, David Miller wrote:
From: Khalid Aziz
Date: Mon, 7 Mar 2016 14:33:56 -0700
On 03/07/2016 12:16 PM, David Miller wrote:
From: Khalid Aziz
Date: Mon, 7 Mar 2016 11:24:54 -0700
Tags can be cleared by user by setting tag to 0. Tags are
automatically cleared by the hardw
On 03/07/2016 04:12 PM, Rob Gardner wrote:
On 03/07/2016 01:33 PM, Khalid Aziz wrote:
That is a possibility but limited in scope. An address range covered
by a single TTE can have large number of tags. Version tags are set on
cacheline. In extreme case, one could set a tag for each set of
64-by
On 03/07/2016 10:24 AM, Khalid Aziz wrote:
Tags can be cleared by user by setting tag to 0. Tags are
automatically cleared by the hardware when the mapping for a virtual
address is removed from TSB (which is why swappable pages are a
problem), so kernel does not have to do it as part of clean
On 03/08/2016 07:58 AM, David Miller wrote:
From: Khalid Aziz
Date: Mon, 7 Mar 2016 13:41:39 -0700
Shared data may not always be backed by a file. My understanding is
one of the use cases is for in-memory databases. This shared space
could also be used to hand off transactions in flight to oth
On 03/08/2016 06:54 AM, Andy Lutomirski wrote:
This makes sense, but I still think the design is poor. If the hacker
gets code execution, then they can trivially brute force the ADI bits.
ADI in this scenario is intended to prevent the attacker from gaining
code execution in the first place
On 03/07/2016 12:16 PM, David Miller wrote:
From: Khalid Aziz
Date: Mon, 7 Mar 2016 11:24:54 -0700
Tags can be cleared by user by setting tag to 0. Tags are
automatically cleared by the hardware when the mapping for a virtual
address is removed from TSB (which is why swappable pages are a
prob
On Mon, Mar 07, 2016 at 07:50:23PM +0100, Wim Van Sebroeck wrote:
> Hi Guenter,
>
> > Hi Wim,
> >
> > On Sun, Mar 06, 2016 at 11:49:56AM +0100, Wim Van Sebroeck wrote:
> > > Hi Guenter,
> > >
> > > > The watchdog infrastructure is currently purely passive, meaning
> > > > it only passes informat
On 03/07/2016 10:39 AM, Khalid Aziz wrote:
On 03/07/2016 11:12 AM, Dave Hansen wrote:
On 03/07/2016 09:53 AM, Andy Lutomirski wrote:
Also, what am I missing? Tying these tags to the physical page seems
like a poor design to me. This seems really awkward to use.
Yeah, can you describe the st
David Howells wrote:
> James Johnston wrote:
>
> > -If CONFIG_MODULE_SIG_FORCE is enabled or enforcemodulesig=1 is
> > supplied on
> > +If CONFIG_MODULE_SIG_FORCE is enabled or module.sig_enforce=1 is
> > +supplied
>
> You're definitely right about the change from enforcemodulesig to
> sig_enf
From: Rob Gardner
Date: Mon, 7 Mar 2016 15:13:31 -0800
> You can easily read ADI tags with a simple ldxa #ASI_MCD_PRIMARY
> instruction.
Awesome!
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From: Khalid Aziz
Date: Mon, 7 Mar 2016 17:21:05 -0700
> Can we enable ADI support for swappable pages in a subsequent update
> after the core functionality is stable on mlock'd pages?
I already said no.
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On Fri, 2016-03-04 at 09:46 +0200, Jani Nikula wrote:
> […]
> If we're talking about the same asciidoctor (http://asciidoctor.org/)
> it's written in ruby but you can apparently run it in JVM using
> JRuby. Calling it Java-based is misleading.
Indeed, I was somewhat imprecise. Thanks to the work m
This patchset adds support for the CoreSight STM IP block.
In the fourth version, comments from various people have been
addressed. Representing configurations where channels are shared
between multiple masterIDs has been kept unchanged from the previous
version because a viable alternative hasn'
From: Mathieu Poirier
Some architecture like ARM assign masterIDs at the HW design
phase. Those are therefore unreachable to users, making masterID
management in the generic STM core irrelevant.
In this kind of configuration channels are shared between masters
rather than being allocated on a p
For some STM hardware (e.g. ARM CoreSight STM), the masterID associated
to a source is set at the hardware level and not user configurable.
Since the masterID information isn't available to SW, introducing
a new value of -1 to reflect this reality.
Signed-off-by: Chunyan Zhang
---
Documentation/
From: Mathieu Poirier
The System Trace Macrocell (STM) is an IP block falling under the
CoreSight umbrella. It's main purpose it so expose stimulus channels
to any system component for the purpose of information logging.
Bindings for this IP block adds a couple of items to the current
mandatory
From: Pratik Patel
This driver adds support for the STM CoreSight IP block, allowing any
system compoment (HW or SW) to log and aggregate messages via a
single entity.
The CoreSight STM exposes an application defined number of channels
called stimulus port. Configuration is done using entries i
"Maciej S. Szmigiero" writes:
> +#ifdef CONFIG_FAT_DEFAULT_UTF8
> + opts->utf8 = is_vfat;
> +#else
> + opts->utf8 = 0;
> +#endif
> +
Maybe, better to use IS_ENABLED(CONFIG_FAT_DEFAULT_UTF8)?
I.e.,
opts->utf8 = IS_ENABLED(CONFIG_FAT_DEFAULT_UTF8) && is_vfat;
Thanks.
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OGAWA H
On 03/07/2016 09:32 AM, Ramesh Shanmugasundaram wrote:
> + /* Ensure channel starts in FD mode */
> + if (!(priv->can.ctrlmode & CAN_CTRLMODE_FD)) {
> + netdev_err(ndev, "enable can fd mode for channel %d\n", ch);
> + goto fail_mode;
> + }
What's the
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