Hi Ganpatrao,
On 11/10/18 17:06, Ganapatrao Kulkarni wrote:
On Thu, Oct 11, 2018 at 2:43 PM Suzuki K Poulose wrote:
Hi Ganapatrao,
On 11/10/18 07:39, Ganapatrao Kulkarni wrote:
+
+/*
+ * We must NOT create groups containing events from multiple hardware PMUs,
+ * although mixing different s
On Thu, Oct 11, 2018 at 2:43 PM Suzuki K Poulose wrote:
>
> Hi Ganapatrao,
>
> On 11/10/18 07:39, Ganapatrao Kulkarni wrote:
> >>> +
> >>> +/*
> >>> + * We must NOT create groups containing events from multiple hardware
> >>> PMUs,
> >>> + * although mixing different software and hardware PMUs is
Hi Ganapatrao,
On 11/10/18 07:39, Ganapatrao Kulkarni wrote:
+
+/*
+ * We must NOT create groups containing events from multiple hardware PMUs,
+ * although mixing different software and hardware PMUs is allowed.
+ */
+static bool thunderx2_uncore_validate_event_group(struct perf_event *event)
+
Hi Suzuki,
On Wed, Oct 10, 2018 at 3:22 PM Suzuki K Poulose wrote:
>
> Hi Ganapatrao,
>
> On 21/06/18 07:33, Ganapatrao Kulkarni wrote:
> > This patch adds a perf driver for the PMU UNCORE devices DDR4 Memory
> > Controller(DMC) and Level 3 Cache(L3C).
> >
> > ThunderX2 has 8 independent DMC PMUs
Hi Ganapatrao,
On 21/06/18 07:33, Ganapatrao Kulkarni wrote:
This patch adds a perf driver for the PMU UNCORE devices DDR4 Memory
Controller(DMC) and Level 3 Cache(L3C).
ThunderX2 has 8 independent DMC PMUs to capture performance events
corresponding to 8 channels of DDR4 Memory Controller and
Hi Pranith,
On Sat, Jul 7, 2018 at 11:22 AM Pranith Kumar wrote:
>
> Hi Ganapatrao,
>
>
> On Wed, Jun 20, 2018 at 11:33 PM, Ganapatrao Kulkarni
> wrote:
>
> > +
> > +enum thunderx2_uncore_l3_events {
> > + L3_EVENT_NONE,
> > + L3_EVENT_NBU_CANCEL,
> > + L3_EVENT_DIB_RETRY,
> >
