Hi Will,
On Mon, Dec 3, 2018 at 5:39 PM Will Deacon wrote:
>
> On Thu, Nov 22, 2018 at 03:04:31AM +, Kulkarni, Ganapatrao wrote:
> > The SoC has PMU support in its L3 cache controller (L3C) and in the
> > DDR4 Memory Controller (DMC).
> >
> > Signed-off-by: Ganapatrao Kulkarni
> > ---
> > D
On Thu, Nov 22, 2018 at 03:04:31AM +, Kulkarni, Ganapatrao wrote:
> The SoC has PMU support in its L3 cache controller (L3C) and in the
> DDR4 Memory Controller (DMC).
>
> Signed-off-by: Ganapatrao Kulkarni
> ---
> Documentation/perf/thunderx2-pmu.txt | 106 +++
> 1 f
The SoC has PMU support in its L3 cache controller (L3C) and in the
DDR4 Memory Controller (DMC).
Signed-off-by: Ganapatrao Kulkarni
---
Documentation/perf/thunderx2-pmu.txt | 106 +++
1 file changed, 106 insertions(+)
create mode 100644 Documentation/perf/thunderx2-pmu.
