> From: Moger, Babu [mailto:babu.mo...@amd.com]
> >> I'm wondering: does that mean the tasks running with this closid
> >> directly access memory without cache? Is there any usage for this
> situation?
>
> Here is the detailed answer to your question from Doug(in CC).
>
> A closid with L3_MASK of
g; Lendacky, Thomas ;
>> l...@kernel.org; j...@8bytes.org; ja...@google.com;
>> vkuzn...@redhat.com; r...@alum.mit.edu; jpoim...@redhat.com; linux-
>> ker...@vger.kernel.org; linux-doc@vger.kernel.org; Yu, Fenghua
>>
>> Subject: RE: [PATCH v7 11/13] arch/x86: Introduce QOS featur
...@redhat.com; linux-
> ker...@vger.kernel.org; linux-doc@vger.kernel.org; Yu, Fenghua
>
> Subject: RE: [PATCH v7 11/13] arch/x86: Introduce QOS feature for AMD
>
> > From: Moger, Babu [mailto:babu.mo...@amd.com]
> > Subject: [PATCH v7 11/13] arch/x86: Introduce QOS fe
> From: Moger, Babu [mailto:babu.mo...@amd.com]
> Subject: [PATCH v7 11/13] arch/x86: Introduce QOS feature for AMD
> The specification for this feature is available at
> https://developer.amd.com/wp-content/resources/56375.pdf
> +bool cbm_validate_amd(char *buf, u32 *data, struct
Enables QOS feature on AMD.
Following QoS sub-features are supported in AMD if the underlying
hardware supports it.
- L3 Cache allocation enforcement
- L3 Cache occupancy monitoring
- L3 Code-Data Prioritization support
- Memory Bandwidth Enforcement(Allocation)
The specification for this feat
