On 01/31/2017 09:38 AM, Will Deacon wrote:
> On Mon, Jan 30, 2017 at 06:08:17PM -0500, Christopher Covington wrote:
>> diff --git a/arch/arm64/include/asm/tlbflush.h
>> b/arch/arm64/include/asm/tlbflush.h
>> index deab52374119..fc434f421c7b 100644
>> --- a/arch/arm64/include/asm/tlbflush.h
>> +++
On Mon, Jan 30, 2017 at 06:08:17PM -0500, Christopher Covington wrote:
> diff --git a/arch/arm64/include/asm/tlbflush.h
> b/arch/arm64/include/asm/tlbflush.h
> index deab52374119..fc434f421c7b 100644
> --- a/arch/arm64/include/asm/tlbflush.h
> +++ b/arch/arm64/include/asm/tlbflush.h
> @@ -36,9 +36
On Tue, Jan 31, 2017 at 12:42:23PM +, Mark Rutland wrote:
> On Mon, Jan 30, 2017 at 06:08:17PM -0500, Christopher Covington wrote:
> > During a TLB invalidate sequence targeting the inner shareable domain,
> > Falkor may prematurely complete the DSB before all loads and stores using
> > the old
On Mon, Jan 30, 2017 at 06:08:17PM -0500, Christopher Covington wrote:
> During a TLB invalidate sequence targeting the inner shareable domain,
> Falkor may prematurely complete the DSB before all loads and stores using
> the old translation are observed. Instruction fetches are not subject to
> th
During a TLB invalidate sequence targeting the inner shareable domain,
Falkor may prematurely complete the DSB before all loads and stores using
the old translation are observed. Instruction fetches are not subject to
the conditions of this erratum. If the original code sequence includes
multiple T
