Re: [PATCH v3 3/6] perf: hisi: Add support for HiSilicon SoC L3C PMU driver

2017-07-20 Thread Zhangshaokun
Hi Jonathan, On 2017/7/19 17:28, Jonathan Cameron wrote: > On Tue, 18 Jul 2017 15:59:56 +0800 > Shaokun Zhang wrote: > >> This patch adds support for L3C PMU driver in HiSilicon SoC chip, Each >> L3C has own control, counter and interrupt registers and is an separate >> PMU. For each L3C PMU, it

Re: [PATCH v3 3/6] perf: hisi: Add support for HiSilicon SoC L3C PMU driver

2017-07-19 Thread Jonathan Cameron
On Tue, 18 Jul 2017 15:59:56 +0800 Shaokun Zhang wrote: > This patch adds support for L3C PMU driver in HiSilicon SoC chip, Each > L3C has own control, counter and interrupt registers and is an separate > PMU. For each L3C PMU, it has 8-programable counters and supports 0x60 > events, event code

[PATCH v3 3/6] perf: hisi: Add support for HiSilicon SoC L3C PMU driver

2017-07-18 Thread Shaokun Zhang
This patch adds support for L3C PMU driver in HiSilicon SoC chip, Each L3C has own control, counter and interrupt registers and is an separate PMU. For each L3C PMU, it has 8-programable counters and supports 0x60 events, event code is 8-bits and every counter is free-running. Interrupt is supporte