On 29/05/2019 09:29, Paolo Bonzini wrote:
On 24/05/19 09:56, Tao Xu wrote:
+
+ if (rdmsrl_safe(MSR_IA32_UMWAIT_CONTROL, &host_umwait_control))
+ return;
+
Does the host value ever change? If not, this can perhaps be read once
when kvm_intel is loaded. And if it changes of
On 24/05/19 09:56, Tao Xu wrote:
> +
> + if (rdmsrl_safe(MSR_IA32_UMWAIT_CONTROL, &host_umwait_control))
> + return;
> +
Does the host value ever change? If not, this can perhaps be read once
when kvm_intel is loaded. And if it changes often, it should be
shadowed into a percpu v
UMWAIT and TPAUSE instructions use IA32_UMWAIT_CONTROL at MSR index E1H
to determines the maximum time in TSC-quanta that the processor can reside
in either C0.1 or C0.2.
This patch is to emulate MSR IA32_UMWAIT_CONTROL in guest and
differentiate MSR_TEST_CTL between host and guest.
Co-developed-
