Hi Timur,
On 27 February 2016 at 03:27, Timur Tabi wrote:
> fu@linaro.org wrote:
>>
>> + if (action) {
>> + irq = platform_get_irq(pdev, 0);
>> + if (irq < 0) {
>> + action = 0;
>> + dev_warn(dev, "unable to get ws0
fu@linaro.org wrote:
+ if (action) {
+ irq = platform_get_irq(pdev, 0);
+ if (irq < 0) {
+ action = 0;
+ dev_warn(dev, "unable to get ws0 interrupt.\n");
+ } else {
+ if (devm_req
On Wed, Feb 17, 2016 at 12:33:24AM +0800, Fu Wei wrote:
[ ... ]
> >>> +MODULE_AUTHOR("Fu Wei ");
> >>> +MODULE_AUTHOR("Suravee Suthikulpanit ");
> >>> +MODULE_AUTHOR("Al Stone ");
> >>> +MODULE_AUTHOR("Timur Tabi ");
> >>> +MODULE_LICENSE("GPL v2");
> >>>
> >> Do you need a MODULE_ALIAS ?
> >
> > F
On 16 February 2016 at 23:54, Fu Wei wrote:
> On 16 February 2016 at 23:29, Guenter Roeck wrote:
>> On 02/16/2016 12:36 AM, fu@linaro.org wrote:
>>>
>>> From: Fu Wei
>>>
>>> According to Server Base System Architecture (SBSA) specification,
>>> the SBSA Generic Watchdog has two stage timeout
On 16 February 2016 at 23:29, Guenter Roeck wrote:
> On 02/16/2016 12:36 AM, fu@linaro.org wrote:
>>
>> From: Fu Wei
>>
>> According to Server Base System Architecture (SBSA) specification,
>> the SBSA Generic Watchdog has two stage timeouts: the first signal (WS0)
>> is for alerting the syst
On 02/16/2016 12:36 AM, fu@linaro.org wrote:
From: Fu Wei
According to Server Base System Architecture (SBSA) specification,
the SBSA Generic Watchdog has two stage timeouts: the first signal (WS0)
is for alerting the system by interrupt, the second one (WS1) is a real
hardware reset.
More
From: Fu Wei
According to Server Base System Architecture (SBSA) specification,
the SBSA Generic Watchdog has two stage timeouts: the first signal (WS0)
is for alerting the system by interrupt, the second one (WS1) is a real
hardware reset.
More details about the hardware specification of this de
