Hi Mark/Will,
Thanks.
On 2017/10/19 23:32, Mark Rutland wrote:
> On Thu, Oct 19, 2017 at 04:28:35PM +0100, Will Deacon wrote:
>> On Thu, Oct 19, 2017 at 01:29:18PM +0100, Mark Rutland wrote:
>>> Will, are you happy to queue this?
>>>
>>> There's a minor fixup [1] needed in patch 2, but otherwise
Hi Mark,
Thanks for your further explanation.
On 2017/10/18 21:55, Mark Rutland wrote:
> On Wed, Oct 18, 2017 at 09:33:30PM +0800, Zhangshaokun wrote:
>> On 2017/10/17 23:16, Mark Rutland wrote:
>>> On Tue, Aug 22, 2017 at 04:07:54PM +0800, Shaokun Zhang wrote
Hi Mark,
On 2017/10/17 23:21, Mark Rutland wrote:
> On Tue, Aug 22, 2017 at 04:07:56PM +0800, Shaokun Zhang wrote:
>> This patch adds support for DDRC PMU driver in HiSilicon SoC chip, Each
>> DDRC has own control, counter and interrupt registers and is an separate
>> PMU. For each DDRC PMU, it ha
Hi Mark,
On 2017/10/17 23:18, Mark Rutland wrote:
> On Tue, Aug 22, 2017 at 04:07:55PM +0800, Shaokun Zhang wrote:
>> L3 cache coherence is maintained by Hydra Home Agent (HHA) in HiSilicon
>> SoC. This patch adds support for HHA PMU driver, Each HHA has own
>> control, counter and interrupt regis
Hi Mark,
On 2017/10/17 23:16, Mark Rutland wrote:
> On Tue, Aug 22, 2017 at 04:07:54PM +0800, Shaokun Zhang wrote:
>> +static int hisi_l3c_pmu_init_irq(struct hisi_pmu *l3c_pmu,
>> + struct platform_device *pdev)
>> +{
>> +int irq, ret;
>> +
>> +/* Read and init
Hi Mark,
Thanks for your comments.
On 2017/10/17 23:06, Mark Rutland wrote:
> Hi,
>
> Apologies for the delay for this review.
>
> Largely this seems to look OK, but there are a couple of things which
> stick out.
>
> On Tue, Aug 22, 2017 at 04:07:53PM +0800, Shaokun Zhang wrote:
>> +int hisi_
Hi All,
Do you have any comments on this patch set?
Thanks,
Shaokun
On 2017/9/21 18:40, Zhangshaokun wrote:
> Hi Mark/Will,
>
> Appreciate any comments from you.
>
> Thanks,
> Shaokun
>
> On 2017/8/22 16:07, Shaokun Zhang wrote:
>> This patchset adds support
Hi Mark/Will,
Appreciate any comments from you.
Thanks,
Shaokun
On 2017/8/22 16:07, Shaokun Zhang wrote:
> This patchset adds support for HiSilicon SoC uncore PMUs driver. It
> includes L3C, Hydra Home Agent (HHA) and DDRC.
>
> Changes in v5:
> * remove unnecessary name/num_events member in his
Hi Mark/Will,
Do you have any comments on this patch set? Appreciate your comments.
Thanks,
Shaokun
On 2017/8/22 16:07, Shaokun Zhang wrote:
> This patchset adds support for HiSilicon SoC uncore PMUs driver. It
> includes L3C, Hydra Home Agent (HHA) and DDRC.
>
> Changes in v5:
> * remove unnec
Hi Mark,
On 2017/8/15 21:02, Mark Rutland wrote:
> On Tue, Jul 25, 2017 at 08:10:41PM +0800, Shaokun Zhang wrote:
>> This patch adds support for DDRC PMU driver in HiSilicon SoC chip, Each
>> DDRC has own control, counter and interrupt registers and is an separate
>> PMU. For each DDRC PMU, it has
Hi Mark,
On 2017/8/15 19:05, Mark Rutland wrote:
> On Tue, Jul 25, 2017 at 08:10:40PM +0800, Shaokun Zhang wrote:
>> +/* HHA register definition */
>> +#define HHA_INT_MASK0x0804
>> +#define HHA_INT_STATUS 0x0808
>> +#define HHA_INT_CLEAR 0x080C
>> +#defi
Hi Mark,
On 2017/8/15 18:41, Mark Rutland wrote:
> On Tue, Jul 25, 2017 at 08:10:39PM +0800, Shaokun Zhang wrote:
>> This patch adds support for L3C PMU driver in HiSilicon SoC chip, Each
>> L3C has own control, counter and interrupt registers and is an separate
>> PMU. For each L3C PMU, it has 8-
Hi Mark,
On 2017/8/15 18:16, Mark Rutland wrote:
> Hi,
>
> On Tue, Jul 25, 2017 at 08:10:38PM +0800, Shaokun Zhang wrote:
>> +/* Read Super CPU cluster and CPU cluster ID from MPIDR_EL1 */
>> +void hisi_read_sccl_and_ccl_id(u32 *sccl_id, u32 *ccl_id)
>> +{
>> +u64 mpidr;
>> +
>> +mpidr =
Hi Mark,
Thanks for your comments.
On 2017/8/15 17:50, Mark Rutland wrote:
> Hi,
>
> On Tue, Jul 25, 2017 at 08:10:37PM +0800, Shaokun Zhang wrote:
>> This patch adds documentation for the uncore PMUs on HiSilicon SoC.
>>
>> Reviewed-by: Jonathan Cameron
>> Signed-off-by: Shaokun Zhang
>> Sign
Hi Mark/Will,
Appreciate your comments.
Thanks.
Shaokun
On 2017/7/25 20:10, Shaokun Zhang wrote:
> This patchset adds support for HiSilicon SoC uncore PMUs driver. It
> includes L3C, Hydra Home Agent (HHA) and DDRC.
>
> Changes in v4:
> * remove redundant code and comments
> * reverse the funct
Hi Jonathan
On 2017/7/20 21:49, Jonathan Cameron wrote:
> On Thu, 20 Jul 2017 21:03:19 +0800
> Zhangshaokun wrote:
>
>> Hi Jonathan
>>
>> On 2017/7/19 17:19, Jonathan Cameron wrote:
>>> On Tue, 18 Jul 2017 15:59:55 +0800
>>> Shaokun Zhang wrote:
Hi Jonathan,
On 2017/7/19 17:28, Jonathan Cameron wrote:
> On Tue, 18 Jul 2017 15:59:56 +0800
> Shaokun Zhang wrote:
>
>> This patch adds support for L3C PMU driver in HiSilicon SoC chip, Each
>> L3C has own control, counter and interrupt registers and is an separate
>> PMU. For each L3C PMU, it
Hi Jonathan
On 2017/7/19 17:19, Jonathan Cameron wrote:
> On Tue, 18 Jul 2017 15:59:55 +0800
> Shaokun Zhang wrote:
>
>> This patch adds support HiSilicon SoC uncore PMU driver framework and
>> interfaces.
>>
>> Signed-off-by: Shaokun Zhang
>> Signed-off-by: Anurup M
> A couple of minor thin
Hi Jonathan,
Thanks for your comments firstly.
On 2017/7/19 17:17, Jonathan Cameron wrote:
> On Tue, 18 Jul 2017 15:59:54 +0800
> Shaokun Zhang wrote:
>
>> This patch adds documentation for the uncore PMUs on HiSilicon SoC.
>>
>> Signed-off-by: Shaokun Zhang
>> Signed-off-by: Anurup M
> Hi
Hi,
On 2017/6/28 9:49, kbuild test robot wrote:
> Hi Shaokun,
>
> [auto build test ERROR on next-20170619]
> [also build test ERROR on v4.12-rc7]
> [cannot apply to linus/master linux/master arm64/for-next/core v4.12-rc6
> v4.12-rc5 v4.12-rc4]
> [if your patch is applied to the wrong git tree, p
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