Re: [PATCH v11 00/14] riscv: Add support for xtheadvector

2024-11-27 Thread Yangyu Chen
Tested-by: Yangyu Chen I applied and tested it on Nezha hardware, and it works fine. Cheers, Yangyu Chen On 11/14/24 10:21, Charlie Jenkins wrote: xtheadvector is a custom extension that is based upon riscv vector version 0.7.1 [1]. All of the vector routines have been modified to support

Re: [PATCH v11 10/14] riscv: hwprobe: Add thead vendor extension probing

2024-11-13 Thread Yangyu Chen
On 11/14/24 12:46, Charlie Jenkins wrote: On Thu, Nov 14, 2024 at 11:26:47AM +0800, Yangyu Chen wrote: On 11/14/24 11:02, Charlie Jenkins wrote: On Thu, Nov 14, 2024 at 10:44:37AM +0800, Yangyu Chen wrote: On 11/14/24 10:21, Charlie Jenkins wrote: Add a new hwprobe key

Re: [PATCH v11 10/14] riscv: hwprobe: Add thead vendor extension probing

2024-11-13 Thread Yangyu Chen
On 11/14/24 11:02, Charlie Jenkins wrote: On Thu, Nov 14, 2024 at 10:44:37AM +0800, Yangyu Chen wrote: On 11/14/24 10:21, Charlie Jenkins wrote: Add a new hwprobe key "RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0" which allows userspace to probe for the new RISCV_ISA_VENDOR_EXT_XT

Re: [PATCH v11 10/14] riscv: hwprobe: Add thead vendor extension probing

2024-11-13 Thread Yangyu Chen
On 11/14/24 10:21, Charlie Jenkins wrote: Add a new hwprobe key "RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0" which allows userspace to probe for the new RISCV_ISA_VENDOR_EXT_XTHEADVECTOR vendor extension. Hi Charlie, How about changing the name of the key from "RISCV_ISA_VENDOR_EXT_XTHEADVECTOR

Re: [PATCH v10 05/14] riscv: vector: Use vlenb from DT for thead

2024-11-09 Thread Yangyu Chen
el panic - not syncing: Fatal exception in interrupt [ 978.937158] ---[ end Kernel panic - not syncing: Fatal exception in interrupt ]--- Is something wrong with my setup? Thanks, Yangyu Chen > + return 0; > + } > + > riscv_v_enable(); > this_vsiz

Re: [PATCH v10 10/14] riscv: hwprobe: Add thead vendor extension probing

2024-10-29 Thread Yangyu Chen
On 9/12/24 13:55, Charlie Jenkins wrote: > Add a new hwprobe key "RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0" which > allows userspace to probe for the new RISCV_ISA_VENDOR_EXT_XTHEADVECTOR > vendor extension. I believe it's more advantageous to use RISCV_HWPROBE_KEY_VENDOR_EXT_0 to ensure that this k

Re: [PATCH 3/3] riscv: mm: Do not restrict mmap address based on hint

2024-09-05 Thread Yangyu Chen
. We should care about what to do to not break userspace on sv57 machines as QEMU enables sv57 by default, which is widely used. > but there's a handful of discussions around that which might take a bit. > >> >> Thanks, >> Yangyu Chen >> >>> Signed