On Thu, 2016-07-28 at 10:21 -0500, atull wrote:
> > >
> > > This isn't going work if more than one bridge is used. Each bridge has
> > > its own priv and thus priv->l3_remap_value. Each bridge's priv will
> > > have just the bit for it's own remap set. The 2nd bridge to be enabled
> > > will tur
On Mon, 2016-06-13 at 14:35 -0500, atull wrote:
> > > +
> > > + /* Allow bridge to be visible to L3 masters or not */
> > > + if (priv->remap_mask) {
> > > + priv->l3_remap_value |= ALT_L3_REMAP_MPUZERO_MSK;
> >
> > Doesn't seem like this belongs here. I realize the write-only register
>
On Fri, 2016-02-05 at 15:30 -0600, at...@opensource.altera.com wrote:
> Supports Altera SOCFPGA bridges:
> * fpga2sdram
> * fpga2hps
> * hps2fpga
> * lwhps2fpga
>
> Allows enabling/disabling the bridges through the FPGA
> Bridge Framework API functions.
I'm replying to v16 because it exists o
