> - PCM output
> - wifi and bt connector reserved.
>
> Board info can find here:
> https://github.com/Axl-zhang/Allwinner-V40-T3-R40-manual
>
> Signed-off-by: Hao Zhang
Applied both patches, thanks!
Maxime
--
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as the Allwinner R40 for In-Car
> Entertainment usage.
That series looks good, thanks! The only thing that would need to be
reworked is your Signed-off-by name, which (I guess?) should be
written the same way than in your Copyright info.
Thanks!
Maxime
--
Maxime Ripard, Bootlin
Embedded Linux
d support for V3s SoC")
> > Signed-off-by: Icenowy Zheng
>
> Maxime,
> Ping. Have you checked this patchset?
Applied, thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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On Tue, Aug 22, 2017 at 01:14:09PM +0800, icen...@aosc.io wrote:
> 在 2017-08-21 17:34，Maxime Ripard 写道：
> > Hi,
> >
> > On Sun, Aug 20, 2017 at 01:29:57PM +0800, Icenowy Zheng wrote:
> > > Allwinner R40 is a new SoC, with Quad Core Cortex-A7 and peripherals
&g
mpat[] = {
> "allwinner,sun8i-h2-plus",
> "allwinner,sun8i-h3",
> "allwinner,sun8i-v3s",
> + "allwinner,sun8i-r40",
And same thing here.
Thanks!
Maxime
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On Thu, May 04, 2017 at 10:45:11PM +0800, Icenowy Zheng wrote:
>
>
> 于 2017年5月4日 GMT+08:00 下午10:41:52, Maxime Ripard
> 写到:
> >On Thu, May 04, 2017 at 10:03:26PM +0800, Icenowy Zheng wrote:
> >>
> >>
> >> 于 2017年5月4日 GMT+08:00 下午10:02:20, Maxime Ri
t; + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + i2c1: i2c@1c2b000 {
> + compatible = "allwinner,sun6i-a31-i2c";
> + reg = <0x01c2b000 0x400>;
> + interrupts = ;
> + clocks = <&ccu CLK_BUS_I2C1>;
> + resets = <&ccu RST_BUS_I2C1>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + i2c2: i2c@1c2b400 {
> + compatible = "allwinner,sun6i-a31-i2c";
> + reg = <0x01c2b400 0x400>;
> + interrupts = ;
> + clocks = <&ccu CLK_BUS_I2C2>;
> + resets = <&ccu RST_BUS_I2C2>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + i2c3: i2c@1c2b800 {
> + compatible = "allwinner,sun6i-a31-i2c";
> + reg = <0x01c2b800 0x400>;
> + interrupts = ;
> + clocks = <&ccu CLK_BUS_I2C3>;
> + resets = <&ccu RST_BUS_I2C3>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + i2c4: i2c@1c2c000 {
> + compatible = "allwinner,sun6i-a31-i2c";
> + reg = <0x01c2c000 0x400>;
> + interrupts = ;
> + clocks = <&ccu CLK_BUS_I2C4>;
> + resets = <&ccu RST_BUS_I2C4>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + gic: interrupt-controller@1c81000 {
> + compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
> + reg = <0x01c81000 0x1000>,
> + <0x01c82000 0x1000>,
> + <0x01c84000 0x2000>,
> + <0x01c86000 0x2000>;
> + interrupt-controller;
> + #interrupt-cells = <3>;
> + interrupts = IRQ_TYPE_LEVEL_HIGH)>;
> + };
> + };
> +
> + timer {
> + compatible = "arm,armv7-timer";
> + interrupts = IRQ_TYPE_LEVEL_LOW)>,
> + IRQ_TYPE_LEVEL_LOW)>,
> + IRQ_TYPE_LEVEL_LOW)>,
> + IRQ_TYPE_LEVEL_LOW)>;
> + clock-frequency = <2400>;
> + arm,cpu-registers-not-fw-configured;
Is it true? U-boot doesn't setup those already?
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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On Thu, May 04, 2017 at 10:07:47PM +0800, Icenowy Zheng wrote:
>
>
> 于 2017年5月4日 GMT+08:00 下午10:04:31, Maxime Ripard
> 写到:
> >On Thu, May 04, 2017 at 09:49:58PM +0800, Icenowy Zheng wrote:
> >> Allwinner A10, A20 and R40 SoCs have similar GPIO layout.
> >>
e = "vdd-sys";
> +};
> +
> +®_dcdc5 {
> + regulator-always-on;
> + regulator-min-microvolt = <150>;
> + regulator-max-microvolt = <150>;
> + regulator-name = "vcc-dram";
> +};
> +
> +®_dldo1 {
> + regulator-min-microvolt = <180>;
> + regulator-max-microvolt = <330>;
> + regulator-name = "vcc-wifi-io";
> +};
> +
> +®_dldo2 {
> + regulator-min-microvolt = <330>;
> + regulator-max-microvolt = <330>;
> + regulator-name = "vcc-wifi";
> +};
> +
> +&mmc0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&mmc0_pins>;
If there is multiple options, then it should be suffixed. If there's
only a single option, then it should be set in the DTSI. Either way,
this is wrong.
Maxime
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Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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On Thu, May 04, 2017 at 10:03:26PM +0800, Icenowy Zheng wrote:
>
>
> 于 2017年5月4日 GMT+08:00 下午10:02:20, Maxime Ripard
> 写到:
> >On Thu, May 04, 2017 at 09:49:59PM +0800, Icenowy Zheng wrote:
> >> static const struct of_device_id sun4i_a10_pinctrl_match[] = {
> &g
_BUS_KEYPAD]= { 0x2d0, BIT(10) },
> + [RST_BUS_I2S0] = { 0x2d0, BIT(12) },
> + [RST_BUS_I2S1] = { 0x2d0, BIT(13) },
> + [RST_BUS_I2S2] = { 0x2d0, BIT(14) },
> +
> + [RST_BUS_I2C0] = { 0x2d8, BIT(0) },
> + [RST_BUS
mit title is misleading since
you're not adding it to the A10 driver. You just adding SoC IDs
definitions
Maxime
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Maxime Ripard, Free Electrons
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http://free-electrons.com
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for the same
device: this driver, and the old one. This is not ok, and probably
introduces some corner cases.
Maxime
--
Maxime Ripard, Free Electrons
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http://free-electrons.com
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On Fri, Jan 20, 2017 at 01:54:43AM +0800, Icenowy Zheng wrote:
> Allwinner V3s SoC has a pin controller like other Allwinner SoCs and got
> supported by the sunxi-pinctrl driver now.
>
> Add a device tree binding for it.
>
> Signed-off-by: Icenowy Zheng
Acked-by: Maxime Ripar
nt branch.
Fixed the conflicts and applied.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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On Fri, Jan 20, 2017 at 01:54:46AM +0800, Icenowy Zheng wrote:
> Allwinner V3s is now driven by sunxi-ng CCU driver.
>
> Add devicetree binding for it.
>
> Signed-off-by: Icenowy Zheng
Applied. Thanks,
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineer
g
> ---
Having a changelog somewhere would help. Why did you drop your cover
letter?
> +static const char * const mbus_parents[] = { "osc24M", "pll-periph0-2x",
> "pll-ddr" };
This is more that 80 characters and triggers a warning in
checkpatch...
Anyway, fix
gt; + };
Did you have the chance to actually test how the RTC was behaving?
Other RTC have been pretty bad at keeping time, this is probably
something you want to check.
Applied,
Maxime
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On Fri, Jan 20, 2017 at 01:54:48AM +0800, Icenowy Zheng wrote:
> Lichee Pi Zero is a small-sized V3s board, which is
> breadboard-compatible, and with a MicroUSB port with both OTG function
> and power function.
>
> Signed-off-by: Icenowy Zheng
Applied, thanks
Maxime
--
Maxi
On Wed, Jan 18, 2017 at 01:02:03AM +0800, Icenowy Zheng wrote:
>
> 2017年1月17日 17:04于 Maxime Ripard 写道：
> >
> > Hi,
> >
> > On Tue, Jan 17, 2017 at 02:01:14AM +0800, Icenowy Zheng wrote:
> > > V3s has a similar but cut-down CCU to H3.
> > >
>
On Wed, Jan 18, 2017 at 01:08:14AM +0800, Icenowy Zheng wrote:
>
>
> 17.01.2017, 17:05, "Maxime Ripard" :
> > Hi,
> >
> > On Tue, Jan 17, 2017 at 02:01:14AM +0800, Icenowy Zheng wrote:
> >> V3s has a similar but cut-down CCU to H3.
> >
ress of V3s datasheet.
>
> Note: the V3s datasheet contains its user manual.
That would be great to use User Manual in the filename rather than
datasheet then. The datasheet is something different.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-el
video")
> - Clocks about CSI largely differs. (As V3s is designed as a camera SoC, and
> it have an extra "pll-isp")
OK.
Thanks,
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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Hi,
On Wed, Jan 11, 2017 at 11:55:16AM +0800, Icenowy Zheng wrote:
>
> 2017年1月11日 02:10于 Maxime Ripard 写道：
> >
> > On Tue, Jan 03, 2017 at 11:16:26PM +0800, Icenowy Zheng wrote:
> > > V3s has a similar but cut-down CCU to H3.
> > >
> > > Ad
1;4601;0c
On Thu, Jan 12, 2017 at 03:40:32AM +0800, Icenowy Zheng wrote:
>
>
> 11.01.2017, 02:09, "Maxime Ripard" :
> > On Tue, Jan 03, 2017 at 11:16:25PM +0800, Icenowy Zheng wrote:
> >> Allwinner V3s is a low-end single-core Cortex-A7 SoC, with 64MB
On Fri, Jan 13, 2017 at 01:31:41AM +0800, Icenowy Zheng wrote:
>
> 2017年1月13日 01:19于 Maxime Ripard 写道：
> >
> > On Thu, Jan 12, 2017 at 03:44:53AM +0800, Icenowy Zheng wrote:
> > >
> > >
> > > 12.01.2017, 03:40, "Icenowy Zheng" :
> &g
On Thu, Jan 12, 2017 at 03:44:53AM +0800, Icenowy Zheng wrote:
>
>
> 12.01.2017, 03:40, "Icenowy Zheng" :
> > 11.01.2017, 02:10, "Maxime Ripard" :
> >> On Tue, Jan 03, 2017 at 11:16:26PM +0800, Icenowy Zheng wrote:
> >>> V3s has a simil
On Wed, Jan 11, 2017 at 11:56:32AM +0800, Icenowy Zheng wrote:
>
> 2017年1月11日 02:21于 Maxime Ripard 写道：
> >
> > On Tue, Jan 03, 2017 at 11:16:28PM +0800, Icenowy Zheng wrote:
> > > + uart0_pins_a: uart0@0 {
> > > + pins = "PB8", "PB9&q
e H3 driver.
Thanks!
Maxime
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Embedded Linux and Kernel engineering
http://free-electrons.com
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On Tue, Jan 03, 2017 at 11:16:27PM +0800, Icenowy Zheng wrote:
> V3s SoC features only a pin controller (for the lack of CPUs part).
>
> Add a driver for this controller.
>
> Signed-off-by: Icenowy Zheng
Acked-by: Maxime Ripard
Thanks,
Maxime
--
Maxime Ripard, Free Electrons
as-pull-up;
Why do you need a pullup here?
Looks good otherwise.
Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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se don't put random links in there, but at least something that we
know will be there in a couple of weeks/monthes/years
Thanks,
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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On Fri, Dec 02, 2016 at 11:05:13PM +0800, Icenowy Zheng wrote:
> Orange Pi Zero is a board that came with the new Allwinner H2+ SoC and a
> SDIO Wi-Fi chip by Allwinner (XR819).
>
> Add a device tree file for it.
>
> Signed-off-by: Icenowy Zheng
Applied, thanks!
Maxime
--
M
On Mon, Dec 05, 2016 at 07:01:46PM +0800, Icenowy Zheng wrote:
>
>
> 05.12.2016, 17:40, "Maxime Ripard" :
> > On Mon, Dec 05, 2016 at 04:59:44PM +0800, Icenowy Zheng wrote:
> >> 2016年12月5日 16:52于 Maxime Ripard 写道：
> >> >
> >> > On
On Fri, Dec 02, 2016 at 10:22:30PM +0800, Icenowy Zheng wrote:
>
>
> 01.12.2016, 17:36, "Maxime Ripard" :
> > On Mon, Nov 28, 2016 at 12:29:07AM +, André Przywara wrote:
> >> > Something more interesting happened.
> >> >
> >> >
On Fri, Dec 02, 2016 at 04:10:46PM +, Andre Przywara wrote:
> Hi,
>
> On 02/12/16 14:32, Icenowy Zheng wrote:
> >
> >
> > 02.12.2016, 22:30, "Hans de Goede" :
> >> Hi,
> >>
> >> On 02-12-16 15:22, Icenowy Zheng wrote:
> >
; >> >
> >> > Add a device tree file for it.
> >> >
> >> > Signed-off-by: Icenowy Zheng <ice...@aosc.xyz>
Please make sure to disable the HTML replies, this is what your mail
looks like on a !HTML MUA :)
Maxime
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Maxime Ripard, Free Electrons
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On Mon, Dec 05, 2016 at 04:59:44PM +0800, Icenowy Zheng wrote:
>
> 2016年12月5日 16:52于 Maxime Ripard 写道：
> >
> > On Fri, Dec 02, 2016 at 10:22:30PM +0800, Icenowy Zheng wrote:
> > >
> > >
> > > 01.12.2016, 17:36, "Maxime Ripard" :
> >
d the alphabetical order in the bindings doc, and applied.
Thanks!
Maxime
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Maxime Ripard, Free Electrons
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of users. And that minority will prevent to do
a proper power management when the times come since we'll have to keep
that behaviour forever.
Maxime
--
Maxime Ripard, Free Electrons
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http://free-electrons.com
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wifi_pwrseq_pin_opi0: wifi_pwrseq_pin@0 {
> >> + allwinner,pins = "PL7";
> >> + allwinner,function = "gpio_out";
> >
> > And same thing here.
>
> Might we do away with the pinmux for gpio pins tradition?
> Recent pat
On Wed, Nov 23, 2016 at 09:23:49AM +, Andre Przywara wrote:
> Hi Maxime,
>
> On 23/11/16 07:57, Maxime Ripard wrote:
> > On Tue, Nov 22, 2016 at 12:24:20AM +0800, Icenowy Zheng wrote:
> >> Orange Pi Zero is a board that came with the new Allwinner H2+ SoC.
> >>
gt; +
> +&ohci1 {
> + status = "okay";
> +};
> +
> +&pio {
> + leds_opi0: led_pins@0 {
> + pins = "PA17";
> + function = "gpio_out";
> + };
> +};
> +
> +&r_pio {
> + leds_r_opi0: led_pins@0 {
> + pins = "PL10";
> + function = "gpio_out";
> + };
> +};
> +
> +&uart0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart0_pins_a>;
> + status = "okay";
> +};
> +
> +&uart1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart1_pins>;
> + status = "disabled";
> +};
> +
> +&uart2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart2_pins>;
> + status = "disabled";
> +};
I'm not sure you answered me on this one. Are those exposed on the
headers? why did you put them as disabled here?
Thanks!
Maxime
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Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
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t; +};
> +
> &ohci1 {
> status = "okay";
> };
> @@ -104,6 +136,11 @@
> pins = "PA17";
> function = "gpio_out";
> };
> +
> + vcc_wifi_pin_opi0: vcc_wifi_pin@0 {
> + allwinner,pins = "PA20&qu
index 4d6467c..26b35a7 100644
> --- a/Documentation/devicetree/bindings/arm/sunxi.txt
> +++ b/Documentation/devicetree/bindings/arm/sunxi.txt
> @@ -13,6 +13,7 @@ using one of the following compatible strings:
>allwinner,sun8i-a33
>allwinner,sun8i-a83t
>allwinner,sun8
> directly to the 5V DC-in jack. So IMHO adding something like
> the fixed reg_vcc5v0 a supply here just makes the dt
> harder to read.
It also makes the regulator tree more complete and accurate because
you'd list all the devices that are needing those regulators. That
would also mak
We'll
create it if we need it at some point.
Maxime
--
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Embedded Linux and Kernel engineering
http://free-electrons.com
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mp;r_pio {
> + leds_r_opi0: led_pins@0 {
> + allwinner,pins = "PL10";
> + allwinner,function = "gpio_out";
> + allwinner,drive = ;
> + allwinner,pull = ;
You can drop the drive and pull properties, and could you use the
gene
+13,6 @@ using one of the following compatible strings:
>allwinner,sun8i-a33
>allwinner,sun8i-a83t
>allwinner,sun8i-h3
> + allwinner,sun8i-h2plus
That's a nitpick, but I'd prefer to have sun8i-h2-plus.
Thanks!
Maxime
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Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
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On Wed, Feb 24, 2016 at 06:45:53PM +0530, Laxman Dewangan wrote:
> Use devm_pinctrl_register() for pin control registration and clean
> the error path.
>
> Signed-off-by: Laxman Dewangan
> Cc: Maxime Ripard
> Cc: Chen-Yu Tsai
Acked-by: Maxime Ripard
Thanks!
Maxime
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M
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