On Tue, Nov 05, 2024 at 09:10:15PM -0800, anish kumar wrote:
> Added overview section which details
> how the remote processor framework works and
> how it handles crashes.
>
> Signed-off-by: anish kumar
> ---
> Documentation/staging/remoteproc.rst | 43
> 1 file cha
On Tue, Nov 05, 2024 at 09:10:14PM -0800, anish kumar wrote:
> Update the intrduction section to add key components
> provided by remote processor framework.
>
> Signed-off-by: anish kumar
> ---
> Documentation/staging/remoteproc.rst | 17 +
> 1 file changed, 17 insertions(+)
>
; V5:
> based on comment from mathieu poirier, remove all files
> and combined that in the original file and as he adviced
> nothing with respect to old documentation was changed.
>
> V4:
> Fixed compilation errors and moved documentation to
> driver-api directory.
>
>
V5:
> based on comment from mathieu poirier, remove all files
> and combined that in the original file and as he adviced
> nothing with respect to old documentation was changed.
>
> V4:
> Fixed compilation errors and moved documentation to
> driver-api directory.
>
&g
On Fri, 25 Oct 2024 at 09:13, anish kumar wrote:
>
> On Fri, Oct 25, 2024 at 7:57 AM Mathieu Poirier
> wrote:
> >
> > On Thu, Oct 24, 2024 at 11:17:40AM -0700, anish kumar wrote:
> > > On Thu, Oct 24, 2024 at 8:53 AM Mathieu Poirier
> > > wrote:
> &
On Thu, Oct 24, 2024 at 11:17:40AM -0700, anish kumar wrote:
> On Thu, Oct 24, 2024 at 8:53 AM Mathieu Poirier
> wrote:
> >
> > On Tue, Oct 22, 2024 at 10:33:53PM -0700, anish kumar wrote:
> > > Added following changes:
> > > 1. Components provided by remot
On Tue, Oct 22, 2024 at 10:33:53PM -0700, anish kumar wrote:
> Added following changes:
> 1. Components provided by remoteproc framework.
> 2. Remoteproc driver responsibilities.
> 3. Remoteproc framework responsibilities.
> 4. Better explanation of how to ask for resources
> from the framework by
On Tue, Oct 22, 2024 at 10:33:51PM -0700, anish kumar wrote:
> In prepration of moving the remoteproc documentation
> from staging to mainline and also for enhancing
> the documentation.
>
> Signed-off-by: anish kumar
> ---
> Documentation/driver-api/index.rst| 1 +
> Documentation/
On Wed, 23 Oct 2024 at 07:53, Jonathan Corbet wrote:
>
> anish kumar writes:
>
> > This patch series transitions the documentation
> > for remoteproc from the staging directory to the
> > mainline kernel. It introduces both kernel and
> > user-space APIs, enhancing the overall documentation
> > q
On Wed, Oct 16, 2024 at 06:11:23PM -0700, anish kumar wrote:
> In preparation of making the documentation
> mainline. Remove the documentation from staging.
>
> Signed-off-by: anish kumar
> ---
> v2:
> | Reported-by: kernel test robot
> | Closes:
> https://lore.kernel.org/oe-kbuild-all/20241016
Hi Anish,
First and foremost, there are kernel bot problems to fix.
On Mon, Oct 14, 2024 at 07:58:31PM -0700, anish kumar wrote:
> Add the documentation in the mainline from
> staging and add the relvant information from
> current mainline.
>
> Added:
> 1. userspace api documentation.
> 2. kerne
Good morning,
This is a case of old english vs. new english. Using "implementors" is still
correct. Moreover, there are 33 instances of the word "implementor" in the
kernel tree. Unless there is an effor to change all occurences I will not move
forward with this patch.
Thanks,
Mathieu
On Tue,
On Sun, Dec 03, 2023 at 12:06:04PM -0800, Adrien Leravat wrote:
> It seems the documentation was not updated when `rpmsg_sendto`
> and related switched from `rpmsg_channel` to `rpmsg_endpoint`.
> This change updates the proper calls, text, and the sample.
>
> Signed-off-by: Adrien Leravat
> ---
>
On Fri, Oct 06, 2023 at 08:38:52PM +0530, Mukesh Ojha wrote:
> Hi Bjorn/Mathieu,
>
> Patches from 2/17-4/17 is just a movement of functions to separate
> config/file.
>
> Do you think, these can be picked independently from this series ?
> I can send them separately, if required.
Bjorn handles
On Fri, 18 Oct 2019 at 10:20, Mathieu Poirier
wrote:
>
> On Tue, Oct 15, 2019 at 10:20:03PM +0100, Mike Leach wrote:
> > There are two files in the Documentation/trace directory relating to
> > coresight, with more to follow, so create a Documentation/trace/coresight
>
gt; +[EVENTCTLR1], if supported [IDR5].
> +
> +
> +**bit (21):**
> +ETM_MODE_ISTALL_EN
> +
> +**description:**
> +Set to enable the ISTALL bit in the stall control register
> +[STALLCTLR]
> +
> +
> +**bit (23):**
> +ETM_MODE_INSTPRIO
> +
> +**description:**
> + Set to enable the INSTPRIORITY bit in the stall control register
> + [STALLCTLR] , if supported [IDR0].
> +
> +
> +**bit (24):**
> +ETM_MODE_NOOVERFLOW
> +
> +**description:**
> +Set to enable the NOOVERFLOW bit in the stall control register
> +[STALLCTLR], if supported [IDR3].
> +
> +
> +**bit (25):**
> +ETM_MODE_TRACE_RESET
> +
> +**description:**
> +Set to enable the TRCRESET bit in the viewinst control register
> +[VICTLR] , if supported [IDR3].
> +
> +
> +**bit (26):**
> +ETM_MODE_TRACE_ERR
> +
> +**description:**
> +Set to enable the TRCCTRL bit in the viewinst control register
> +[VICTLR].
> +
> +
> +**bit (27):**
> +ETM_MODE_VIEWINST_STARTSTOP
> +
> +**description:**
> +Set the initial state value of the ViewInst start / stop logic
> +in the viewinst control register [VICTLR]
> +
> +
> +**bit (30):**
> +ETM_MODE_EXCL_KERN
> +
> +**description:**
> +Set default trace setup to exclude kernel mode trace (see note a)
> +
> +
> +**bit (31):**
> +ETM_MODE_EXCL_USER
> +
> +**description:**
> +Set default trace setup to exclude user space trace (see note a)
> +
> +
> +
> +*Note a)* On startup the ETM is programmed to trace the complete address
> space
> +using address range comparator 0. ‘mode’ bits 30 / 31 modify this setting to
> +set EL exclude bits for NS state in either user space (EL0) or kernel space
> +(EL1) in the address range comparator. (the default setting excludes all
> +secure EL, and NS EL2)
> +
> +Once the reset parameter has been used, and/or custom programming has been
> +implemented - using these bits will result in the EL bits for address
> +comparator 0 being set in the same way.
> +
> +*Note b)* Bits 2-3, 8-10, 15-16, 18, 22, control features that only work with
> +data trace. As A-profile data trace is architecturally prohibited in ETMv4,
> +these have been omitted here. Possible uses could be where a kernel has
> +support for control of R or M profile infrastructure as part of a
> heterogeneous
> +system.
> +
> +Bits 17, 28-29 are unused.
This is quite usefull - thanks for putting it together:
Reviewed-by: Mathieu Poirier
> --
> 2.17.1
>
; F: Documentation/devicetree/bindings/arm/coresight.txt
> F: Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt
> F: Documentation/ABI/testing/sysfs-bus-coresight-devices-*
Reviewed-by: Mathieu Poirier
> --
> 2.17.1
>
on
that more than one patch is needed. This case is somewhat on the fence since
changes are trivial.
Since Jonathan maintains the documentation subsystem the decision is left to
him. Whether Jonathan wants the patch split or will simply take it as is:
Reviewed-by: Mathieu Poirier
>
> S
On Tue, Oct 15, 2019 at 10:20:01PM +0100, Mike Leach wrote:
> An API to control single-shot comparator operation was missing from sysfs.
> This adds the parameters to sysfs to allow programming of this feature.
>
> Signed-off-by: Mike Leach
> ---
> .../coresight/coresight-etm4x-sysfs.c |
On Thu, 17 Oct 2019 at 12:00, Mathieu Poirier
wrote:
>
> On Tue, Oct 15, 2019 at 10:19:56PM +0100, Mike Leach wrote:
> > TRCACATRn registers have match bits for secure and non-secure exception
> > levels which are not accessible by the sysfs API.
> > This adds a new sysfs
On Tue, Oct 15, 2019 at 10:19:56PM +0100, Mike Leach wrote:
> TRCACATRn registers have match bits for secure and non-secure exception
> levels which are not accessible by the sysfs API.
> This adds a new sysfs parameter to enable this - addr_exlevel_s_ns.
>
> Reviewed-by: Suzuki K Poulose
> Signe
rect mask value - register has two
> event values.
> 3) cyc_threshold_store() - must mask with max before checking min
> otherwise wrapped values can set illegal value below min.
> 4) res_ctrl_store() - update to mask off all res0 bits.
>
> Reviewed-by: Leo Yan
> Reviewed-by: Ma
Hi Mike,
On Tue, Oct 15, 2019 at 10:19:54PM +0100, Mike Leach wrote:
> ETMv4.4 adds in support for tracing secure EL2 (per arch 8.x updates).
> Patch accounts for this new capability.
>
> Reviewed-by: Leo Yan
> Signed-off-by: Mike Leach
> ---
> .../hwtracing/coresight/coresight-etm4x-sysfs.c
On Wed, 4 Sep 2019 at 10:17, Greg KH wrote:
>
> On Wed, Sep 04, 2019 at 10:05:51AM -0600, Mathieu Poirier wrote:
> > On Tue, 3 Sep 2019 at 23:48, Greg KH wrote:
> > >
> > > On Tue, Sep 03, 2019 at 04:51:40PM -0600, Mathieu Poirier wrote:
> > > > O
On Tue, 3 Sep 2019 at 16:47, Mike Leach wrote:
>
> Hi Mathieu,
>
> On Tue, 3 Sep 2019 at 20:38, Mathieu Poirier
> wrote:
> >
> > Hi Mike,
> >
> > On Thu, Aug 29, 2019 at 10:33:21PM +0100, Mike Leach wrote:
> > > Add in detailed progra
On Tue, 3 Sep 2019 at 23:48, Greg KH wrote:
>
> On Tue, Sep 03, 2019 at 04:51:40PM -0600, Mathieu Poirier wrote:
> > On Tue, 3 Sep 2019 at 13:59, Greg KH wrote:
> > >
> > > On Thu, Aug 29, 2019 at 10:33:19PM +0100, Mike Leach wrote:
> > > > Update docume
On Tue, 3 Sep 2019 at 13:59, Greg KH wrote:
>
> On Thu, Aug 29, 2019 at 10:33:19PM +0100, Mike Leach wrote:
> > Update document to include the new sysfs features added during this
> > patchset.
> >
> > Updated to reflect the new sysfs component nameing schema.
> >
> > Signed-off-by: Mike Leach
>
ices/etm/enable_source
> Date: April 2015
> KernelVersion: 4.01
> Contact:Mathieu Poirier
> @@ -8,82 +8,82 @@ Description:(RW) Enable/disable tracing on this
> specific trace entiry.
> of coresight components linking the source to the si
Hi Mike,
On Thu, Aug 29, 2019 at 10:33:21PM +0100, Mike Leach wrote:
> Add in detailed programmers reference for users wanting to program the
> CoreSight ETM 4.x driver using sysfs.
>
> Signed-off-by: Mike Leach
> ---
> .../coresight/coresight-etm4x-reference.txt | 458 ++
> 1
below the minimum requirements.
> Signed-off-by: Phong Tran
As for the content of the patch:
Acked-by: Mathieu Poirier
> ---
> ChangeLog:
> V2: review points from Mathieu, Jonathan
> * Add coresight-cpu-debug
> * Update MAINTAINERS file
> * Avoid use markup as m
coresight.txt
> +++ b/Documentation/trace/coresight.rst
> @@ -1,5 +1,6 @@
> - Coresight - HW Assisted Tracing on ARM
> - ==
> +==
> +Coresight - HW Assisted Tracing on ARM
> +=
got changed in commit 7d83d17795ef ("coresight: tmc: adding sysFS
> management entries").
>
> Cc: Mathieu Poirier
> Cc: Randy Dunlap
> Cc: Jonathan Corbet
> Signed-off-by: Kim Phillips
I'm good with this version - Jonathan, should I take this through my
tree of yo
got changed in commit 7d83d17795ef ("coresight: tmc: adding sysFS
> management entries").
>
> Cc: Mathieu Poirier
> Cc: Jonathan Corbet
> Signed-off-by: Kim Phillips
> ---
> Documentation/trace/coresight.txt | 40 ++-
> 1 file chan
mal value.
>
> So this commit removes useless %px and update section "Output format"
> in the document for alignment between the code and document.
>
> Suggested-by: Kees Cook
> Cc: Mathieu Poirier
> Signed-off-by: Leo Yan
Applied - thanks,
Mathieu
> ---
&
Adding a section that document how to use the Coresight framework and
drivers from the perf tools.
Signed-off-by: Mathieu Poirier
---
Documentation/trace/coresight.txt | 52 ++-
1 file changed, 51 insertions(+), 1 deletion(-)
diff --git a/Documentation/trace
This patch groups together section pertaining to the perf tools. That way
everything is at the same place rather than spread out.
Signed-off-by: Mathieu Poirier
---
Documentation/trace/coresight.txt | 72 +++
1 file changed, 36 insertions(+), 36 deletions
Field "owner" of struct coresight_desc has been removed a while back but
the documentation was not updated to reflect the changes.
Signed-off-by: Mathieu Poirier
---
Documentation/trace/coresight.txt | 3 ---
1 file changed, 3 deletions(-)
diff --git a/Documentation/trace/coresi
Now that the perf tools CoreSight support is upstream this set adds
documentation to go with it and move things around so that topics
are located together.
Changes for V2:
* Addressed grammatical problems highlighted by Randy
Mathieu Poirier (3):
coresight: Remove obsolete reference
On 16 April 2018 at 13:48, Randy Dunlap wrote:
> On 04/16/2018 12:35 PM, Mathieu Poirier wrote:
>> Adding a section that document how to use the Coresight framework and
>> drivers from the perf tools.
>>
>> Signed-off-by: Mathieu Poirier
>> ---
>>
Field "owner" of struct coresight_desc has been removed a while back but
the documentation was not updated to reflect the changes.
Signed-off-by: Mathieu Poirier
---
Documentation/trace/coresight.txt | 3 ---
1 file changed, 3 deletions(-)
diff --git a/Documentation/trace/coresi
Adding a section that document how to use the Coresight framework and
drivers from the perf tools.
Signed-off-by: Mathieu Poirier
---
Documentation/trace/coresight.txt | 50 +++
1 file changed, 50 insertions(+)
diff --git a/Documentation/trace/coresight.txt
Now that the perf tools CoreSight support is upstream this set adds
documentation to go with it and move things around so that topics
are located together.
Mathieu Poirier (3):
coresight: Remove obsolete reference to "owner" in CoreSight
descriptor
coresight: Add section for i
This patch groups together section pertaining to the perf tools. That way
everything is at the same place rather than spread out.
Signed-off-by: Mathieu Poirier
---
Documentation/trace/coresight.txt | 72 +++
1 file changed, 36 insertions(+), 36 deletions
r the
> corresponding kdump node at initialization and won't be cleared anymore.
>
> Suggested-by: Mathieu Poirier
> Signed-off-by: Leo Yan
> ---
> drivers/hwtracing/coresight/coresight-etm4x.c | 27
> +++
> drivers/hwtracing/coresight/cor
On Fri, Mar 30, 2018 at 11:15:23AM +0800, Leo Yan wrote:
> If Coresight path is enabled for specific CPU, the sink device handler
> need to be set to kdump node; on the other hand we also need to clear
> sink device handler when path is disabled.
>
> This patch sets sink devices handler for kdump
On Fri, Mar 30, 2018 at 11:15:22AM +0800, Leo Yan wrote:
> Since Coresight panic kdump functionality has been ready, this patch is
> to hook panic callback function for ETB/ETF driver. The driver data
> structure has allocated a buffer when the session started, so simply
> save tracing data into t
On Fri, Mar 30, 2018 at 11:15:21AM +0800, Leo Yan wrote:
> After kernel panic happens, Coresight tracing data has much useful info
> which can be used for analysis. For example, the trace info from ETB
> RAM can be used to check the CPU execution flows before the crash. So
> we can save the traci
what's usage.
>
> Credits to Mathieu Poirier for many suggestions since the first version
> patch reviewing. The suggestions include using an array to manage dump
> related info, this makes code scalable for more CPUs; the Coresight
> kdump driver and integration kdump flow with oth
Hi Leo,
Please see below (and in upcoming patches) my comments related to your latest
work.
Thanks,
Mathieu
On Fri, Mar 30, 2018 at 11:15:18AM +0800, Leo Yan wrote:
> This patch set is to explore Coresight tracing data for postmortem
> debugging. When kernel panic happens, the Coresight panic k
On 9 January 2018 at 22:33, Leo Yan wrote:
> On Tue, Jan 09, 2018 at 01:21:28PM -0700, Mathieu Poirier wrote:
>> On Thu, Dec 21, 2017 at 04:20:15PM +0800, Leo Yan wrote:
>> > ETMv4 hardware information and configuration needs to be saved as
>> > metadata; these metadat
On 9 January 2018 at 22:19, Leo Yan wrote:
> On Tue, Jan 09, 2018 at 11:41:26AM -0700, Mathieu Poirier wrote:
>> On Thu, Dec 21, 2017 at 04:20:12PM +0800, Leo Yan wrote:
>> > After kernel panic happens, coresight has many useful info can be used
>> > for analysis.
buffer info,
> this can avoid unnecessary list addition and deletion operations.
> Removal of the tracers from the dump list is done in function
> free_event_data().
>
> Suggested-by: Mathieu Poirier
> Signed-off-by: Leo Yan
> ---
> drivers/hwtracing/coresight/co
On Thu, Dec 21, 2017 at 04:20:12PM +0800, Leo Yan wrote:
> After kernel panic happens, coresight has many useful info can be used
> for analysis. For example, the trace info from ETB RAM can be used to
> check the CPU execution flows before crash. So we can save the tracing
> data from sink devic
c@vger.kernel.org
> Cc: Tommaso Cucinotta
> Cc: Mathieu Poirier
> ---
Please add a short description for your change, even if it is trivial.
> Documentation/scheduler/sched-deadline.txt | 13 ++---
> 1 file changed, 10 insertions(+), 3 deletions(-)
>
> diff --g
#x27;exec' to access '/dev/cpu_dma_latency', the
> command 'exec' can avoid the file descriptor to be closed so we can
> keep the constraint on cpu_dma_latency.
>
> This patch also adds the info for reference docs for PM QoS and cpuidle
> sysfs.
>
> Cc: Jo
#x27;exec' to access '/dev/cpu_dma_latency', the
> command 'exec' can avoid the file descriptor to be closed so we can
> keep the constraint on cpu_dma_latency.
>
> This patch also adds the info for reference docs for PM QoS and cpuidle
> sysfs.
>
&
On 5 June 2017 at 02:33, Wei Xu wrote:
> Hi Leo,
>
> On 2017/5/25 16:57, Leo Yan wrote:
>> Bind debug module driver for Hi6220.
>>
>> Reviewed-by: Mathieu Poirier
>> Signed-off-by: Leo Yan
>
> Thanks!
> Fine to me.
> Acked-by: Wei Xu
>
> Hi
Poulose's patch to fix issue for the func
> of_get_coresight_platform_data() doesn't properly drop the reference
> to the CPU node pointer.
> * According to Suzuki suggestion, added code to handl the corner case
> for ARMv8 CPU with aarch32 mode.
> * According to S
On 23 May 2017 at 08:16, Leo Yan wrote:
> Coresight includes debug module and usually the module connects with CPU
> debug logic. ARMv8 architecture reference manual (ARM DDI 0487A.k) has
> description for related info in "Part H: External Debug".
>
> Chapter H7 "The Sample-based Profiling Extensi
On 23 May 2017 at 08:16, Leo Yan wrote:
> Add debug unit on Qualcomm msm8916 based platforms, including the
> DragonBoard 410c board.
>
> Reviewed-by: Mathieu Poirier
> Signed-off-by: Leo Yan
Andy and David,
Would you mind taking a look a this when you have a minute? If it
On 23 May 2017 at 08:16, Leo Yan wrote:
> Bind debug module driver for Hi6220.
>
> Reviewed-by: Mathieu Poirier
> Signed-off-by: Leo Yan
Wei and Mark,
I think it makes sense to have this go through the coresight tree
along with the rest of the driver. Please have a look and
On Tue, May 09, 2017 at 10:49:57AM +0800, Leo Yan wrote:
> Update document file entries for Coresight debug module.
>
> Signed-off-by: Leo Yan
Reviewed-by: Mathieu Poirier
> ---
> MAINTAINERS | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/MAINTAINE
On Tue, May 09, 2017 at 10:49:56AM +0800, Leo Yan wrote:
> Add coresight_cpu_debug.enable to kernel-parameters.txt, this flag is
> used to enable/disable the CPU sampling based debugging.
>
> Signed-off-by: Leo Yan
Reviewed-by: Mathieu Poirier
> ---
> Documentation/
o enable the debugging functionality are provided.
>
> Suggested-by: Mike Leach
> Signed-off-by: Leo Yan
Reviewed-by: Mathieu Poirier
> ---
> Documentation/trace/coresight-cpu-debug.txt | 174
>
> 1 file changed, 174 insertions(+)
> create
On Tue, May 09, 2017 at 10:50:02AM +0800, Leo Yan wrote:
> Add debug unit on Qualcomm msm8916 based platforms, including the
> DragonBoard 410c board.
>
> Signed-off-by: Leo Yan
Reviewed-by: Mathieu Poirier
> ---
> arch/arm64/boot/dts/qcom
On Tue, May 09, 2017 at 10:50:01AM +0800, Leo Yan wrote:
> Bind debug module driver for Hi6220.
>
> Signed-off-by: Leo Yan
Reviewed-by: Mathieu Poirier
> ---
> arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 64
> +++
> 1 file changed, 64 in
On Tue, May 09, 2017 at 10:50:00AM +0800, Leo Yan wrote:
> Coresight includes debug module and usually the module connects with CPU
> debug logic. ARMv8 architecture reference manual (ARM DDI 0487A.k) has
> description for related info in "Part H: External Debug".
>
> Chapter H7 "The Sample-based
On 5 May 2017 at 09:04, Sudeep Holla wrote:
>
>
> On 05/05/17 15:48, Mathieu Poirier wrote:
>> On Fri, May 05, 2017 at 02:55:17PM +0100, Sudeep Holla wrote:
>
> [...]
>
>>>
>>> Just curious as why this is not registered under coresight bus using
>>
On Fri, May 05, 2017 at 02:55:17PM +0100, Sudeep Holla wrote:
>
>
> On 02/05/17 11:08, Leo Yan wrote:
> > Coresight includes debug module and usually the module connects with CPU
> > debug logic. ARMv8 architecture reference manual (ARM DDI 0487A.k) has
> > description for related info in "Part H
On Tue, May 02, 2017 at 06:08:32PM +0800, Leo Yan wrote:
> Update kernel-parameters.txt to add new parameter:
> coresight_cpu_debug.enable is a knob to enable debugging at boot time.
>
> Add detailed documentation, which contains the implementation, Mike
> Leach excellent summary for "clock and po
On Tue, May 02, 2017 at 06:08:35PM +0800, Leo Yan wrote:
> Coresight includes debug module and usually the module connects with CPU
> debug logic. ARMv8 architecture reference manual (ARM DDI 0487A.k) has
> description for related info in "Part H: External Debug".
>
> Chapter H7 "The Sample-based
On 21 April 2017 at 08:12, Alex Shi wrote:
> The rt-mutex-design documents didn't gotten meaningful update from its
> first version. Even after owner's pending bit was removed in commit
> 8161239a8bcc
> ("rtmutex: Simplify PI algorithm and make highest prio task get lock")
> and priority list 'pl
On 6 April 2017 at 07:30, Leo Yan wrote:
> Coresight includes debug module and usually the module connects with CPU
> debug logic. ARMv8 architecture reference manual (ARM DDI 0487A.k) has
> description for related info in "Part H: External Debug".
>
> Chapter H7 "The Sample-based Profiling Extens
On 6 April 2017 at 07:30, Leo Yan wrote:
> Update kernel-parameters.txt to add new parameter:
> coresight_cpu_debug.enable is a knob to enable debugging at boot time.
>
> Add detailed documentation, which contains the implementation, Mike
> Leach excellent summary for "clock and power domain". At
On 19 April 2017 at 09:30, Leo Yan wrote:
> On Wed, Apr 19, 2017 at 08:52:12AM -0600, Mathieu Poirier wrote:
>
> [...]
>
>> >> > +static bool debug_enable;
>> >> > +module_param_named(enable, debug_enable, bool, 0600);
>> >> > +MOD
On 18 April 2017 at 18:18, Leo Yan wrote:
> On Tue, Apr 18, 2017 at 11:40:50AM -0600, Mathieu Poirier wrote:
>> On Thu, Apr 06, 2017 at 09:30:59PM +0800, Leo Yan wrote:
>> > Coresight includes debug module and usually the module connects with CPU
>> > debug logic. A
On Thu, Apr 06, 2017 at 09:30:59PM +0800, Leo Yan wrote:
> Coresight includes debug module and usually the module connects with CPU
> debug logic. ARMv8 architecture reference manual (ARM DDI 0487A.k) has
> description for related info in "Part H: External Debug".
>
> Chapter H7 "The Sample-based
On Thu, Apr 06, 2017 at 09:30:58PM +0800, Leo Yan wrote:
> Almost low level functions from open firmware have used const to
> qualify device_node structures, so add const for device_node
> parameters in of_coresight related functions.
>
> Reviewed-by: Stephen Boyd
> Signed-off-by: Leo Yan
I agr
t_platform_data.
>
> This patch also introduces another minor fix is to use
> of_cpu_device_node_get() to replace of_get_cpu_node().
>
> Cc: Mathieu Poirier
> Signed-off-by: Suzuki K Poulose
> [Leo: minor tweaks for of_get_coresight_platform_data]
> Signed-off-by: Leo Y
On 29 March 2017 at 19:59, Leo Yan wrote:
> On Wed, Mar 29, 2017 at 10:55:35AM -0600, Mathieu Poirier wrote:
>
> [...]
>
>> > So this is why add "idle_constraint" as a central place to control
>> > power domain for CPU debug purpose and I also think this i
On Wed, Mar 29, 2017 at 09:54:23AM +0800, Leo Yan wrote:
> Hi Mathieu,
>
> On Tue, Mar 28, 2017 at 10:50:10AM -0600, Mathieu Poirier wrote:
> > On Sun, Mar 26, 2017 at 02:23:14AM +0800, Leo Yan wrote:
>
> [...]
>
> > > +static void debug_force_cpu_powered
On Wed, Mar 29, 2017 at 11:07:35AM +0800, Leo Yan wrote:
> Hi Suzuki,
>
> On Mon, Mar 27, 2017 at 05:34:57PM +0100, Suzuki K Poulose wrote:
> > On 25/03/17 18:23, Leo Yan wrote:
>
> [...]
>
> > Leo,
> >
> > Thanks a lot for the quick rework. I don't fully understand (yet!) why we
> > need the
Hi Leo,
On Sun, Mar 26, 2017 at 02:23:14AM +0800, Leo Yan wrote:
> Coresight includes debug module and usually the module connects with CPU
> debug logic. ARMv8 architecture reference manual (ARM DDI 0487A.k) has
> description for related info in "Part H: External Debug".
>
> Chapter H7 "The Samp
To reduce the amount of traces generated by tracers range
and start/stop address filtering has been implemented. This
patch provides example on how to use the various options
currently supported.
Signed-off-by: Mathieu Poirier
Cc: linux-doc@vger.kernel.org
---
Documentation/trace/coresight.txt
unc() has been moved to the header file.
> - Calculate the channel number according to the channel memory space size.
>
>
> Thanks,
> Chunyan
>
> [1] https://lkml.org/lkml/2016/2/4/652
> [2] https://lkml.org/lkml/2016/2/12/397
> [3] https://lkml.org/lkml/2015/12/22/
On 31 March 2016 at 07:20, Alexander Shishkin
wrote:
> Mathieu Poirier writes:
>
>> On 21 March 2016 at 01:47, Alexander Shishkin
>> wrote:
>>> Chunyan Zhang writes:
>>>
>>>> From: Mathieu Poirier
>>>>
>>>> Some archit
er according to the channel memory space size.
>
>
> Thanks,
> Chunyan
>
> [1] https://lkml.org/lkml/2016/2/4/652
> [2] https://lkml.org/lkml/2016/2/12/397
> [3] https://lkml.org/lkml/2015/12/22/348
>
> Chunyan Zhang (1):
> Documentations: Add explanations of the
ed number of channels
> called stimulus port. Configuration is done using entries in sysfs
> and channels made available to userspace via configfs.
>
> Signed-off-by: Pratik Patel
> Signed-off-by: Mathieu Poirier
> Signed-off-by: Chunyan Zhang
> ---
> .../ABI/tes
On 21 March 2016 at 01:47, Alexander Shishkin
wrote:
> Chunyan Zhang writes:
>
>> From: Mathieu Poirier
>>
>> Some architecture like ARM assign masterIDs at the HW design
>> phase. Those are therefore unreachable to users, making masterID
>> managemen
On 12 February 2016 at 13:33, Mathieu Poirier
wrote:
> On 12 February 2016 at 09:27, Alexander Shishkin
> wrote:
>> Mathieu Poirier writes:
>>
>>> On 8 February 2016 at 06:26, Alexander Shishkin
>>> wrote:
>>>> This $end==$start situation its
On 12 February 2016 at 09:27, Alexander Shishkin
wrote:
> Mathieu Poirier writes:
>
>> On 8 February 2016 at 06:26, Alexander Shishkin
>> wrote:
>>> This $end==$start situation itself may be ambiguous and can be
>>> interpreted either as having just one *st
On 12 February 2016 at 08:28, Alexander Shishkin
wrote:
> Chunyan Zhang writes:
>
>> +static long stm_generic_set_options(struct stm_data *stm_data,
>> + unsigned int master,
>> + unsigned int channel,
>> +
On 12 February 2016 at 08:18, Alexander Shishkin
wrote:
> Chunyan Zhang writes:
>
>> There is already an interface of set_options, but no get_options yet.
>> Before setting any options, one would may want to see the current
>> status of that option by means of get_options interface. This
>> inter
On 12 February 2016 at 07:55, Michael Williams wrote:
> Mathieu Poirier [mailto:mathieu.poir...@linaro.org] wrote:
>> On 6 February 2016 at 04:04, Chunyan Zhang wrote:
>>> From: Pratik Patel
>>>
>>> This driver adds support for the STM CoreSight IP block, a
ion defined number of channels
> called stimulus port. Configuration is done using entries in sysfs
> and channels made available to userspace via configfs.
>
> Signed-off-by: Pratik Patel
> Signed-off-by: Mathieu Poirier
> Signed-off-by: Chunyan Zhang
> ---
> .../ABI/tes
= platform_get_drvdata(pdev);
> +
> + watchdog_unregister_device(&gwdt->wdd);
> +
> + return 0;
> +}
> +
> +/* Disable watchdog if it is active during suspend */
> +static int __maybe_unused sbsa_gwdt_suspend(struct device *dev)
> +{
> + struct sbsa_gwd
On 8 February 2016 at 10:44, Al Grant wrote:
>> Mike did write "master IDs are hardwired to individual cores and core
>> security
>> states", which make assignment for one platform very static.
>> On the flip side those will change from one system to another.
>
> It depends on your perspective.
On 8 February 2016 at 06:26, Alexander Shishkin
wrote:
> Mathieu Poirier writes:
>
>> On 5 February 2016 at 05:52, Alexander Shishkin
>> wrote:
>>> Chunyan Zhang writes:
>>>
>>>> From: Mathieu Poirier
>>>>
>>>> Some archi
On 5 February 2016 at 05:52, Alexander Shishkin
wrote:
> Chunyan Zhang writes:
>
>> From: Mathieu Poirier
>>
>> Some architecture like ARM assign masterIDs statically at the HW design
>> phase, making masterID manipulation in the generic STM core irrelevant.
>&g
On 3 February 2016 at 10:18, wrote:
> From: Fu Wei
>
> This patch registers the WS0 interrupt routine to trigger panic,
> when the watchdog reachs the first stage (the half timeout).
> This function can help administrator to backup the system context
> info by panic console output or kdump (if s
1 - 100 of 108 matches
Mail list logo
