On Fri, Jan 17, 2025 at 11:34:09AM +, Mark Rutland wrote:
> I think we need to fix that before we extend this logic for SME.
Based on some off list discussion I gather you're working on some fixes
including this?
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On Mon, Jan 13, 2025 at 09:51:01AM -0500, Steven Rostedt wrote:
> Geert Uytterhoeven wrote:
> > $ git help fixes
> > 'fixes' is aliased to 'show --format='Fixes: %h ("%s")' -s'
> Hmm, I've just been manually adding the Fixes tags ;-) That's because when
> I add a fixes tag, I also do a more in d
On Sun, Jan 12, 2025 at 10:47:02AM -0500, Neal Gompa wrote:
> On Sun, Jan 12, 2025 at 10:30 AM Miguel Ojeda wrote:
> > +Finally, while providing tags is welcome and typically very appreciated,
> > please
> > +note that signers (i.e. submitters and maintainers) may use their
> > discretion in
>
ction rather than supporting a missing test.
The sigill functions aren't well sorted in the file so the ordering is a
bit random.
Signed-off-by: Mark Brown
---
tools/testing/selftests/arm64/abi/hwcap.c | 235 +-
1 file changed, 233 insertions(+), 2 deletions(-)
di
ID_AA64ISAR3_EL1 is currently marked as unallocated in KVM but does have a
number of bitfields defined in it. Expose FPRCVT and FAMINMAX, two simple
instruction only extensions to guests.
Reviewed-by: Marc Zyngier
Signed-off-by: Mark Brown
---
arch/arm64/kvm/sys_regs.c | 6 +-
1 file
The 2024 dpISA introduces a number of architecture features all of which
only add new instructions so only require the addition of hwcaps and ID
register visibility.
Signed-off-by: Mark Brown
---
Documentation/arch/arm64/elf_hwcaps.rst | 50 +
arch/arm64/include
DDI0601 2024-12 introduces SME 2.2 as well as a few new optional features,
update sysreg to reflect the changes in ID_AA64SMFR0_EL1 enumerating them.
Signed-off-by: Mark Brown
---
arch/arm64/tools/sysreg | 26 --
1 file changed, 24 insertions(+), 2 deletions(-)
diff
R0_EL1.SVE
being non-zero. The HWCAPS documentation is amended to reflect the
actually checks performed by the kernel.
Fixes: 06a916feca2b ("arm64: Expose SVE2 features for userspace")
Reported-by: Catalin Marinas
Signed-off-by: Marc Zyngier
Signed-off-by: Mark Brown
Cc: Will Deacon
userspace.
Signed-off-by: Mark Brown
---
Changes in v5:
- Rebase onto arm64/for-next/cpufeature, which incorporates most of the
sysreg updates from earlier versions.
- Remove SF8MM8 and SF8MM4 register defintitions which were removed from
the ISA in the 2024-12 XML release, along with their
On Tue, Jan 07, 2025 at 03:13:24PM +, Will Deacon wrote:
> On Wed, Dec 11, 2024 at 01:02:50AM +0000, Mark Brown wrote:
> > -Res0 27:0
> > +UnsignedEnum 27 SF8MM8
> > + 0b0 NI
> > + 0b1 IMP
> > +EndEnum
> > +UnsignedEnum
Provide a __sme_restore_state() for the hypervisor to allow it to restore
ZA and ZT for guests.
Signed-off-by: Mark Brown
---
arch/arm64/include/asm/kvm_hyp.h | 2 ++
arch/arm64/kvm/hyp/fpsimd.S | 16
2 files changed, 18 insertions(+)
diff --git a/arch/arm64/include/asm
ensures that we exit
streaming mode before running the guest. This ensures that guests do not
receive unexpected SME exceptions.
Signed-off-by: Mark Brown
---
arch/arm64/include/asm/kvm_emulate.h | 4 ++--
arch/arm64/kvm/handle_exit.c | 14 ++
arch/arm64/kvm/hyp/nvhe/hyp-main.c
r frequent accesses.
There is also an EL2 register SMPRIMAP_EL2 for virtualisation of
priorities, this is also RAZ when priority configuration is not
supported but has no specific traps available.
Signed-off-by: Mark Brown
---
arch/arm64/include/asm/kvm_host.h | 2 ++
arch/arm64/include/asm/vncr
Add coverage of the SME ID registers to set_id_regs, ID_AA64PFR1_EL1.SME
becomes writable and we add ID_AA64SMFR_EL1 and it's subfields.
Signed-off-by: Mark Brown
---
tools/testing/selftests/kvm/aarch64/set_id_regs.c | 29 +--
1 file changed, 27 insertions(+), 2 dele
the guest floating point state may be
accessed via the V registers.
Any VMM that supports SME must be aware of the need to configure streaming
mode prior to writing the floating point registers that this creates.
Signed-off-by: Mark Brown
---
arch/arm64/include/asm/kvm_host.h | 9 +++--
arch
SME adds a number of new system registers, update get-reg-list to check for
them based on the visibility of SME.
Signed-off-by: Mark Brown
---
tools/testing/selftests/kvm/aarch64/get-reg-list.c | 32 +-
1 file changed, 31 insertions(+), 1 deletion(-)
diff --git a/tools
SVE or SME is finalised and the
other not, avoiding complexity.
Signed-off-by: Mark Brown
---
arch/arm64/include/asm/kvm_host.h | 1 +
arch/arm64/include/uapi/asm/kvm.h | 1 +
arch/arm64/kvm/arm.c | 10
arch/arm64/kvm/reset.c| 114
extensions adding more
ZT registers. This encoding can readily support such an extension if one is
introduced.
Signed-off-by: Mark Brown
---
arch/arm64/include/asm/kvm_host.h | 19 +++
arch/arm64/include/uapi/asm/kvm.h | 17 ++
arch/arm64/kvm/guest.c| 114
to move the
restore of the effective VL for nested guests to a separate restore
function run after loading the floating point register state, along with
the similar handling required for SME.
The selection of which vector length to use is handled by vcpu_sve_pffr().
Signed-off-by: Mark Brown
registers stub register
access functions are provided that only allow VL configuration. These
will be extended as the SME specific registers, as for SVE.
Signed-off-by: Mark Brown
---
arch/arm64/include/asm/kvm_host.h | 7 +++
arch/arm64/include/uapi/asm/kvm.h | 9
arch/arm64/kvm/guest.c
As for SVE we will need to pull parts of dynamically sized registers out of
a block of memory for SME so we will use a similar code pattern for this.
Rename the current struct sve_state_reg_region in preparation for this.
No functional change.
Signed-off-by: Mark Brown
---
arch/arm64/kvm
purely software defined.
Expose the register as a system register if the guest supports SME,
context switching it along with the other EL0 TPIDRs.
Signed-off-by: Mark Brown
---
arch/arm64/include/asm/kvm_host.h | 1 +
arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h | 15
priorities however we do not
currently have any support for SME priorities and mask that support out
from guests. The intention is to revist this once we have physical
implementations and can properly evaluate the practical impacts that
they have.
Signed-off-by: Mark Brown
---
arch/arm64/include/asm
running on,
this may present issues for asymmetric systems or for migration as it
does for the existing registers.
Signed-off-by: Mark Brown
---
arch/arm64/include/asm/kvm_host.h | 1 +
arch/arm64/kvm/sys_regs.c | 46 ---
2 files changed, 44 insertions(+), 3
clean as might be.
No functional change.
Signed-off-by: Mark Brown
---
arch/arm64/include/asm/kvm_host.h | 17 +++--
arch/arm64/include/asm/kvm_hyp.h| 2 +-
arch/arm64/include/asm/kvm_pkvm.h | 2 +-
arch/arm64/kvm/fpsimd.c | 2 +-
arch/arm64/kvm
The SVE portion of kvm_vcpu_put() is quite large, especially given the
comments required. When we add similar handling for SME the function
will get even larger, in order to keep things managable factor the SVE
portion out of the main kvm_vcpu_put().
Signed-off-by: Mark Brown
---
arch/arm64
h are configured via the normal ID register scheme.
Signed-off-by: Mark Brown
---
arch/arm64/include/asm/kvm_host.h | 23 +--
arch/arm64/kvm/sys_regs.c | 2 +-
2 files changed, 22 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/include/asm/kvm_host.h
b/arch/
.
Signed-off-by: Mark Brown
---
Documentation/virt/kvm/api.rst | 117 +
1 file changed, 82 insertions(+), 35 deletions(-)
diff --git a/Documentation/virt/kvm/api.rst b/Documentation/virt/kvm/api.rst
index
454c2aaa155e5b994ee1f68502d8fdf55cf6700a
the existing KVM_ARM_VCPU_SVE capability, existing
code which does not enable SME will be unaffected and any SME only code
will not need to use SVE constants.
No functional change.
Signed-off-by: Mark Brown
---
arch/arm64/include/asm/kvm_host.h | 6 --
arch/arm64/include/uapi/asm/kvm.h | 6
In preparation for SME support move the macros used to access SVE state
after the feature test macros, we will need to test for SME subfeatures to
determine the size of the SME state.
Signed-off-by: Mark Brown
---
arch/arm64/include/asm/kvm_host.h | 46 +++
1
g the overwhelmingly common case).
Signed-off-by: Mark Brown
---
arch/arm64/include/asm/kvm_host.h | 6 ++
arch/arm64/kvm/hyp/include/hyp/switch.h | 7 ---
2 files changed, 10 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/include/asm/kvm_host.h
b/arch/arm64/include/asm/kvm_h
Rather than add earlier prototypes of specific ctxt_has_ helpers let's just
pull all their definitions to the top of sysreg-sr.h so they're all
available to all the individual save/restore functions.
Signed-off-by: Mark Brown
---
arch/arm64/kvm/hyp/include/hyp/sysreg
happens with a maximum vector length of -1.
Signed-off-by: Mark Brown
---
arch/arm64/kernel/fpsimd.c | 23 ++-
1 file changed, 22 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/kernel/fpsimd.c b/arch/arm64/kernel/fpsimd.c
index
a6f9a102fadb0547b4988cb5b0c239ca90a262a0
multiple updates of the system register.
Convert the function to a static inline so that it can accept runtime
variable arguments.
Signed-off-by: Mark Brown
---
arch/arm64/include/asm/kvm_emulate.h | 27 +--
1 file changed, 9 insertions(+), 18 deletions(-)
diff --git a
variable to
the cpu_fp_state which uses the enable bits in SMCR_ELx to flag which
features are enabled.
Signed-off-by: Mark Brown
---
arch/arm64/include/asm/fpsimd.h | 1 +
arch/arm64/kernel/fpsimd.c | 10 --
arch/arm64/kvm/fpsimd.c | 1 +
3 files changed, 10 insertions
-off-by: Mark Brown
---
arch/arm64/kernel/fpsimd.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/kernel/fpsimd.c b/arch/arm64/kernel/fpsimd.c
index
7c66ed6e43c34d1b5e1cc00595c12244d13d3d0d..a6f9a102fadb0547b4988cb5b0c239ca90a262a0
100644
--- a/arch/arm64
this should be negligable in the
context of the state load or access trap.
Signed-off-by: Mark Brown
---
arch/arm64/include/asm/fpsimd.h | 12 +++
arch/arm64/kernel/cpufeature.c | 2 --
arch/arm64/kernel/fpsimd.c | 44 -
3 files changed, 25 inser
dded
separately.
The series is based on Fuad's series:
https://lore.kernel.org/r/20241216105057.579031-1-ta...@google.com/
It will need a rebase on:
https://lore.kernel.org/r/20241219173351.1123087-1-...@kernel.org
(as will Fuad's.)
Signed-off-by: Mark Brown
---
Changes in v3
On Thu, Dec 19, 2024 at 04:39:11PM +, Mark Brown wrote:
> On Thu, Dec 19, 2024 at 03:55:48PM +, Will Deacon wrote:
> > On Thu, Dec 12, 2024 at 11:33:05AM +0000, Mark Brown wrote:
> > > That'd be useful, yes - unfortunately I think that's still something I
>
On Thu, Dec 19, 2024 at 03:55:48PM +, Will Deacon wrote:
> On Thu, Dec 12, 2024 at 11:33:05AM +0000, Mark Brown wrote:
> > That'd be useful, yes - unfortunately I think that's still something I
> > can't work on myself at the moment for the above mentioned no
On Wed, Dec 11, 2024 at 10:40:15PM +, Will Deacon wrote:
> On Tue, Dec 10, 2024 at 06:43:05PM +0000, Mark Brown wrote:
> > Yes, the issues here are not technical ones. Though there are some
> > complications - eg, IIRC the XML doesn't encode the signedness of
>
The 2024 dpISA introduces a number of architecture features all of which
only add new instructions so only require the addition of hwcaps and ID
register visibility.
Signed-off-by: Mark Brown
---
Documentation/arch/arm64/elf_hwcaps.rst | 51 +
arch/arm64/include
ID_AA64ISAR3_EL1 is currently marked as unallocated in KVM but does have a
number of bitfields defined in it. Expose FPRCVT and FAMINMAX, two simple
instruction only extensions to guests.
Signed-off-by: Mark Brown
---
arch/arm64/kvm/sys_regs.c | 6 +-
1 file changed, 5 insertions(+), 1
ction rather than supporting a missing test.
The sigill functions aren't well sorted in the file so the ordering is a
bit random.
Signed-off-by: Mark Brown
---
tools/testing/selftests/arm64/abi/hwcap.c | 273 +-
1 file changed, 271 insertions(+), 2 deletions(-)
di
DDI0601 2024-09 introduces new features which are enumerated via
ID_AA64ISAR2_EL1, update the sysreg file to reflect these updates.
Signed-off-by: Mark Brown
---
arch/arm64/tools/sysreg | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/tools/sysreg b/arch/arm64
DDI0601 2024-09 introduces SME 2.2 as well as a few new optional features,
update sysreg to reflect the changes in ID_AA64SMFR0_EL1 enumerating them.
Signed-off-by: Mark Brown
---
arch/arm64/tools/sysreg | 32 +++-
1 file changed, 31 insertions(+), 1 deletion
DDI0601 2024-09 introduces SVE 2.2 as well as a few new optional features,
update sysreg to reflect the changes in ID_AA64ZFR0_EL1 enumerating them.
Signed-off-by: Mark Brown
---
arch/arm64/tools/sysreg | 14 --
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/arch
DDI0601 2024-09 defines two new feature flags in ID_AA64FPFR0_EL1
describing new FP8 operations, describe them in sysreg.
Signed-off-by: Mark Brown
---
arch/arm64/tools/sysreg | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/tools/sysreg b/arch/arm64
DDI0601 2024-09 defines a new feature flags in ID_AA64PFR2_EL1
describing support for injecting UNDEF exceptions, update sysreg to
include this.
Signed-off-by: Mark Brown
---
arch/arm64/tools/sysreg | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/tools
DDI0601 2024-09 defines several new feature flags in ID_AA64ISAR3_EL1,
update our description in sysreg to reflect these.
Signed-off-by: Mark Brown
---
arch/arm64/tools/sysreg | 18 +-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/tools/sysreg b/arch
userspace.
Signed-off-by: Mark Brown
---
Changes in v4:
- Fix encodings for ID_AA64ISAR3_EL1.
- Link to v3:
https://lore.kernel.org/r/20241203-arm64-2024-dpisa-v3-0-a6c78b1aa...@kernel.org
Changes in v3:
- Commit log update for the hwcap test.
- Link to v2:
https://lore.kernel.org/r/20241030-arm64
On Tue, Dec 10, 2024 at 05:09:55PM +, Will Deacon wrote:
> Can we _please_ just generate this stuff. It feels like we've been
> making silly typos over and over again with the current approach so
> either it's hard or we're not very good at it. Either way, it should be
> automated.
> Others h
ID_AA64ISAR3_EL1 is currently marked as unallocated in KVM but does have a
number of bitfields defined in it. Expose FPRCVT and FAMINMAX, two simple
instruction only extensions to guests.
Signed-off-by: Mark Brown
---
arch/arm64/kvm/sys_regs.c | 6 +-
1 file changed, 5 insertions(+), 1
ction rather than supporting a missing test.
The sigill functions aren't well sorted in the file so the ordering is a
bit random.
Signed-off-by: Mark Brown
---
tools/testing/selftests/arm64/abi/hwcap.c | 273 +-
1 file changed, 271 insertions(+), 2 deletions(-)
di
DDI0601 2024-09 introduces SME 2.2 as well as a few new optional features,
update sysreg to reflect the changes in ID_AA64SMFR0_EL1 enumerating them.
Signed-off-by: Mark Brown
---
arch/arm64/tools/sysreg | 32 +++-
1 file changed, 31 insertions(+), 1 deletion
DDI0601 2024-09 introduces SVE 2.2 as well as a few new optional features,
update sysreg to reflect the changes in ID_AA64ZFR0_EL1 enumerating them.
Signed-off-by: Mark Brown
---
arch/arm64/tools/sysreg | 14 --
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/arch
userspace.
Signed-off-by: Mark Brown
---
Changes in v3:
- Commit log update for the hwcap test.
- Link to v2:
https://lore.kernel.org/r/20241030-arm64-2024-dpisa-v2-0-b6601a15d...@kernel.org
Changes in v2:
- Filter KVM guest visible bitfields in ID_AA64ISAR3_EL1 to only those
we make writeable
The 2024 dpISA introduces a number of architecture features all of which
only add new instructions so only require the addition of hwcaps and ID
register visibility.
Signed-off-by: Mark Brown
---
Documentation/arch/arm64/elf_hwcaps.rst | 51 +
arch/arm64/include
DDI0601 2024-09 introduces new features which are enumerated via
ID_AA64ISAR2_EL1, update the sysreg file to reflect these updates.
Signed-off-by: Mark Brown
---
arch/arm64/tools/sysreg | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/tools/sysreg b/arch/arm64
DDI0601 2024-09 defines several new feature flags in ID_AA64ISAR3_EL1,
update our description in sysreg to reflect these.
Signed-off-by: Mark Brown
---
arch/arm64/tools/sysreg | 18 +-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/tools/sysreg b/arch
DDI0601 2024-09 defines two new feature flags in ID_AA64FPFR0_EL1
describing new FP8 operations, describe them in sysreg.
Signed-off-by: Mark Brown
---
arch/arm64/tools/sysreg | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/tools/sysreg b/arch/arm64
DDI0601 2024-09 defines a new feature flags in ID_AA64PFR2_EL1
describing support for injecting UNDEF exceptions, update sysreg to
include this.
Signed-off-by: Mark Brown
---
arch/arm64/tools/sysreg | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/tools
DDI0601 2024-09 introduces new features which are enumerated via
ID_AA64ISAR2_EL1, update the sysreg file to reflect these updates.
Signed-off-by: Mark Brown
---
arch/arm64/tools/sysreg | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/tools/sysreg b/arch/arm64
x27;t well sorted in the file so the ordering is a
bit random.
Signed-off-by: Mark Brown
---
tools/testing/selftests/arm64/abi/hwcap.c | 273 +-
1 file changed, 271 insertions(+), 2 deletions(-)
diff --git a/tools/testing/selftests/arm64/abi/hwcap.c
b/tools/testing/selft
ID_AA64ISAR3_EL1 is currently marked as unallocated in KVM but does have a
number of bitfields defined in it. Expose FPRCVT and FAMINMAX, two simple
instruction only extensions to guests.
Signed-off-by: Mark Brown
---
arch/arm64/kvm/sys_regs.c | 6 +-
1 file changed, 5 insertions(+), 1
The 2024 dpISA introduces a number of architecture features all of which
only add new instructions so only require the addition of hwcaps and ID
register visibility.
Signed-off-by: Mark Brown
---
Documentation/arch/arm64/elf_hwcaps.rst | 51 +
arch/arm64/include
DDI0601 2024-09 introduces SVE 2.2 as well as a few new optional features,
update sysreg to reflect the changes in ID_AA64ZFR0_EL1 enumerating them.
Signed-off-by: Mark Brown
---
arch/arm64/tools/sysreg | 14 --
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/arch
DDI0601 2024-09 introduces SME 2.2 as well as a few new optional features,
update sysreg to reflect the changes in ID_AA64SMFR0_EL1 enumerating them.
Signed-off-by: Mark Brown
---
arch/arm64/tools/sysreg | 32 +++-
1 file changed, 31 insertions(+), 1 deletion
DDI0601 2024-09 defines several new feature flags in ID_AA64ISAR3_EL1,
update our description in sysreg to reflect these.
Signed-off-by: Mark Brown
---
arch/arm64/tools/sysreg | 18 +-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/tools/sysreg b/arch
DDI0601 2024-09 defines two new feature flags in ID_AA64FPFR0_EL1
describing new FP8 operations, describe them in sysreg.
Signed-off-by: Mark Brown
---
arch/arm64/tools/sysreg | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/tools/sysreg b/arch/arm64
userspace.
Signed-off-by: Mark Brown
---
Changes in v2:
- Filter KVM guest visible bitfields in ID_AA64ISAR3_EL1 to only those
we make writeable.
- Link to v1:
https://lore.kernel.org/r/20241028-arm64-2024-dpisa-v1-0-a38d08b00...@kernel.org
---
Mark Brown (9):
arm64/sysreg: Update
DDI0601 2024-09 defines a new feature flags in ID_AA64PFR2_EL1
describing support for injecting UNDEF exceptions, update sysreg to
include this.
Signed-off-by: Mark Brown
---
arch/arm64/tools/sysreg | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/tools
On Tue, Oct 29, 2024 at 04:45:00PM +, Marc Zyngier wrote:
> Mark Brown wrote:
> > + ID_WRITABLE(ID_AA64ISAR3_EL1, (ID_AA64ISAR3_EL1_FPRCVT |
> > + ID_AA64ISAR3_EL1_FAMINMAX)),
> Please add the required sanitisation of the register so th
x27;t well sorted in the file so the ordering is a
bit random.
Signed-off-by: Mark Brown
---
tools/testing/selftests/arm64/abi/hwcap.c | 273 +-
1 file changed, 271 insertions(+), 2 deletions(-)
diff --git a/tools/testing/selftests/arm64/abi/hwcap.c
b/tools/testing/selft
DDI0601 2024-09 defines two new feature flags in ID_AA64FPFR0_EL1
describing new FP8 operations, describe them in sysreg.
Signed-off-by: Mark Brown
---
arch/arm64/tools/sysreg | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/tools/sysreg b/arch/arm64
DDI0601 2024-09 defines a new feature flags in ID_AA64PFR2_EL1
describing support for injecting UNDEF exceptions, update sysreg to
include this.
Signed-off-by: Mark Brown
---
arch/arm64/tools/sysreg | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/tools
DDI0601 2024-09 introduces new features which are enumerated via
ID_AA64ISAR2_EL1, update the sysreg file to reflect these updates.
Signed-off-by: Mark Brown
---
arch/arm64/tools/sysreg | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/tools/sysreg b/arch/arm64
The 2024 dpISA introduces a number of architecture features all of which
only add new instructions so only require the addition of hwcaps and ID
register visibility.
Signed-off-by: Mark Brown
---
Documentation/arch/arm64/elf_hwcaps.rst | 51 +
arch/arm64/include
DDI0601 2024-09 defines several new feature flags in ID_AA64ISAR3_EL1,
update our description in sysreg to reflect these.
Signed-off-by: Mark Brown
---
arch/arm64/tools/sysreg | 18 +-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/tools/sysreg b/arch
ID_AA64ISAR3_EL1 is currently marked as unallocated in KVM but does have a
number of bitfields defined in it. Expose FPRCVT and FAMINMAX, two simple
instruction only extensions to guests.
Signed-off-by: Mark Brown
---
arch/arm64/kvm/sys_regs.c | 3 ++-
1 file changed, 2 insertions(+), 1
DDI0601 2024-09 introduces SME 2.2 as well as a few new optional features,
update sysreg to reflect the changes in ID_AA64SMFR0_EL1 enumerating them.
Signed-off-by: Mark Brown
---
arch/arm64/tools/sysreg | 32 +++-
1 file changed, 31 insertions(+), 1 deletion
DDI0601 2024-09 introduces SVE 2.2 as well as a few new optional features,
update sysreg to reflect the changes in ID_AA64ZFR0_EL1 enumerating them.
Signed-off-by: Mark Brown
---
arch/arm64/tools/sysreg | 14 --
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/arch
userspace.
Signed-off-by: Mark Brown
---
Mark Brown (9):
arm64/sysreg: Update ID_AA64PFR2_EL1 to DDI0601 2024-09
arm64/sysreg: Update ID_AA64ISAR3_EL1 to DDI0601 2024-09
arm64/sysreg: Update ID_AA64FPFR0_EL1 to DDI0601 2024-09
arm64/sysreg: Update ID_AA64ZFR0_EL1 to DDI0601
On Fri, Oct 11, 2024 at 01:44:55PM +0800, Zong Li wrote:
> On Wed, Oct 9, 2024 at 7:46 AM Deepak Gupta wrote:
> > + if (si->si_code == SEGV_CPERR) {
> Hi Deepak,
> I got some errors when building this test, I suppose they should be
> fixed in the next version.
> riscv_cfi_test.c: In funct
On Tue, Oct 08, 2024 at 03:37:01PM -0700, Deepak Gupta wrote:
> +int arch_lock_shadow_stack_status(struct task_struct *task,
> + unsigned long arg)
> +{
> + /* If shtstk not supported or not enabled on task, nothing to lock here
> */
> + if (!cpu_supports_shado
On Tue, Oct 08, 2024 at 03:36:48PM -0700, Deepak Gupta wrote:
> riscv will need an implementation for exit_thread to clean up shadow stack
> when thread exits. If current thread had shadow stack enabled, shadow
> stack is allocated by default for any new thread.
FWIW both arm64 and x86 do this vi
On Tue, Oct 08, 2024 at 03:36:44PM -0700, Deepak Gupta wrote:
> VM_SHADOW_STACK (alias to VM_HIGH_ARCH_5) is used to encode shadow stack
> VMA on three architectures (x86 shadow stack, arm GCS and RISC-V shadow
> stack). In case architecture doesn't implement shadow stack, it's VM_NONE
> Introducin
l
> stack (GCS) [6] which are very similar to risc-v's zicfiss shadow stack.
> x86 already supports shadow stack for user mode and arm64 support for GCS in
> usermode [7] is ongoing.
FWIW the arm64 support is now in -next, including these:
> Mark Brown (2):
> mm: In
> memory operand to perform control transfer in program. As part of this
> tracking on indirect branches, CPU goes in a state where it expects a
> landing pad instr on target and if not found then CPU raises some fault
> (architecture dependent)
Reviewed-by: Mark Brown
signature
On Tue, Oct 08, 2024 at 10:55:29PM +, Edgecombe, Rick P wrote:
> A lot of this patch and the previous one is similar to x86's and arm's. It
> great
> that we can have consistency around this behavior.
> There might be enough consistency to refactor some of the arch code into a
> kernel/shstk
On Sat, Oct 05, 2024 at 03:02:09PM +0100, Marc Zyngier wrote:
> Mark Brown wrote:
> > Ah, I see. I'd been under the impression that the generic machinery was
> > supposed to handle this already using the descriptions in
> > emulate-nested.c and we only needed handlers
On Sat, Oct 05, 2024 at 01:36:09PM +0100, Marc Zyngier wrote:
> Mark Brown wrote:
> > + // PSTATE.EXLOCK is set to 0 upon any exception to a higher
> > + // EL, or to GCSCR_ELx.EXLOCKEN for an exception to the same
> > + // exception level. See ARM DDI 0487 R
On Sat, Oct 05, 2024 at 02:18:57PM +0100, Marc Zyngier wrote:
> Mark Brown wrote:
> > On Sat, Oct 05, 2024 at 12:34:20PM +0100, Marc Zyngier wrote:
> > > Where is the handling of traps resulting of HFGITR_EL2.nGCSSTR_EL1?
> > These will trap with an EC of 0x2d wh
On Sat, Oct 05, 2024 at 12:34:20PM +0100, Marc Zyngier wrote:
> Mark Brown wrote:
> > + if (!kvm_has_gcs(kvm)) {
> > + kvm->arch.fgu[HFGxTR_GROUP] |= (HFGxTR_EL2_nGCS_EL0 |
> > + HFGxTR_EL2_nGCS_EL1);
>
GCS adds new registers GCSCR_EL1, GCSCRE0_EL1, GCSPR_EL1 and GCSPR_EL0. Add
these to those validated by get-reg-list.
Reviewed-by: Thiago Jung Bauermann
Signed-off-by: Mark Brown
---
tools/testing/selftests/kvm/aarch64/get-reg-list.c | 28 ++
1 file changed, 28 insertions
As per DDI 0487 RWTXBY we need to manage PSTATE.EXLOCK when entering an
exception, when the exception is entered from a lower EL the bit is cleared
while if entering from the same EL it is set to GCSCR_ELx.EXLOCKEN.
Implement this behaviour in enter_exception64().
Signed-off-by: Mark Brown
deliberately conservative choice to avoid errors due to oversights.
Further fields should be made writable in future.
Signed-off-by: Mark Brown
---
arch/arm64/include/asm/kvm_host.h | 12
arch/arm64/include/asm/vncr_mapping.h | 2 ++
arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h
The initial EL2 setup for GCS did not include disabling of EL1 usage of
GCS instructions, also disable these traps. This is the first disabling
of instruction traps, use x2 to store the value to be written.
Signed-off-by: Mark Brown
---
arch/arm64/include/asm/el2_setup.h | 7 ++-
1 file
S1POE but removed S1PIE, meaning that the extension is no longer visible
to guests. Reenable support for S1PIE with VMM control.
Fixes: 70ed7238297f ("KVM: arm64: Sanitise ID_AA64MMFR3_EL1")
Signed-off-by: Mark Brown
---
arch/arm64/kvm/sys_regs.c | 4 +++-
1 file changed, 3 insertions(+),
h has also been sent separately as this
feature is a dependency for GCS. It is based on:
https://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux.git for-next/gcs
Signed-off-by: Mark Brown
---
Changes in v14:
- Rebase onto arm64/for-next/gcs which includes all the non-KVM support.
- Manag
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