[PATCH v11 2/2] ThunderX2, perf : Add Cavium ThunderX2 SoC UNCORE PMU driver

This patch adds a perf driver for the PMU UNCORE devices DDR4 Memory Controller(DMC) and Level 3 Cache(L3C). Each PMU supports up to 4 counters. All counters lack overflow interrupt and are sampled periodically. Reviewed-by: Suzuki K Poulose Signed-off-by: Ganapatrao Kulkarni --- drivers/perf/K

[PATCH v11 1/2] perf, uncore: Adding documentation for ThunderX2 pmu uncore driver

The SoC has PMU support in its L3 cache controller (L3C) and in the DDR4 Memory Controller (DMC). Signed-off-by: Ganapatrao Kulkarni --- Documentation/perf/thunderx2-pmu.txt | 93 1 file changed, 93 insertions(+) create mode 100644 Documentation/perf/thunderx2-pmu.t

[PATCH v11 0/2] Add ThunderX2 SoC Performance Monitoring Unit driver

This patchset adds PMU driver for Cavium's ThunderX2 SoC UNCORE devices. The SoC has PMU support in L3 cache controller (L3C) and in the DDR4 Memory Controller (DMC). v11: Updated Patch 2 with minor comments. v10: Updated Documentation patch with comments [6]. [6] https://lkml.o

[PATCH v10 2/2] ThunderX2, perf : Add Cavium ThunderX2 SoC UNCORE PMU driver

This patch adds a perf driver for the PMU UNCORE devices DDR4 Memory Controller(DMC) and Level 3 Cache(L3C). Each PMU supports up to 4 counters. All counters lack overflow interrupt and are sampled periodically. Signed-off-by: Ganapatrao Kulkarni --- drivers/perf/Kconfig | 9 + drivers

[PATCH v10 0/2] Add ThunderX2 SoC Performance Monitoring Unit driver

This patchset adds PMU driver for Cavium's ThunderX2 SoC UNCORE devices. The SoC has PMU support in L3 cache controller (L3C) and in the DDR4 Memory Controller (DMC). v10: Updated Documentation patch with comments [6]. [6] https://lkml.org/lkml/2018/12/5/649 v9: Updated with comm

[PATCH v10 1/2] perf, uncore: Adding documentation for ThunderX2 pmu uncore driver

The SoC has PMU support in its L3 cache controller (L3C) and in the DDR4 Memory Controller (DMC). Signed-off-by: Ganapatrao Kulkarni --- Documentation/perf/thunderx2-pmu.txt | 93 1 file changed, 93 insertions(+) create mode 100644 Documentation/perf/thunderx2-pmu.t

[PATCH v9 0/2] Add ThunderX2 SoC Performance Monitoring Unit driver

From: Ganapatrao Kulkarni This patchset adds PMU driver for Cavium's ThunderX2 SoC UNCORE devices. The SoC has PMU support in L3 cache controller (L3C) and in the DDR4 Memory Controller (DMC). v9: Updated with comments [5]. [5] https://lkml.org/lkml/2018/11/22/517 v8: Updated w

[PATCH v9 1/2] perf, uncore: Adding documentation for ThunderX2 pmu uncore driver

The SoC has PMU support in its L3 cache controller (L3C) and in the DDR4 Memory Controller (DMC). Signed-off-by: Ganapatrao Kulkarni --- Documentation/perf/thunderx2-pmu.txt | 93 1 file changed, 93 insertions(+) create mode 100644 Documentation/perf/thunderx2-pmu.t

[PATCH v9 2/2] ThunderX2, perf : Add Cavium ThunderX2 SoC UNCORE PMU driver

This patch adds a perf driver for the PMU UNCORE devices DDR4 Memory Controller(DMC) and Level 3 Cache(L3C). Each PMU supports up to 4 counters. All counters lack overflow interrupt and are sampled periodically. Signed-off-by: Ganapatrao Kulkarni --- drivers/perf/Kconfig | 9 + drivers

[PATCH v8 0/2] Add ThunderX2 SoC Performance Monitoring Unit driver

This patchset adds PMU driver for Cavium's ThunderX2 SoC UNCORE devices. The SoC has PMU support in L3 cache controller (L3C) and in the DDR4 Memory Controller (DMC). v8: Updated with Comments [4] [4] https://lkml.org/lkml/2018/10/25/215 v7: Incorporated review comments [3].

[PATCH v8 1/2] perf, uncore: Adding documentation for ThunderX2 pmu uncore driver

The SoC has PMU support in its L3 cache controller (L3C) and in the DDR4 Memory Controller (DMC). Signed-off-by: Ganapatrao Kulkarni --- Documentation/perf/thunderx2-pmu.txt | 106 +++ 1 file changed, 106 insertions(+) create mode 100644 Documentation/perf/thunderx2-pmu.

[PATCH v8 2/2] ThunderX2, perf : Add Cavium ThunderX2 SoC UNCORE PMU driver

This patch adds a perf driver for the PMU UNCORE devices DDR4 Memory Controller(DMC) and Level 3 Cache(L3C). Each PMU supports up to 4 counters. All counters lack overflow interrupt and are sampled periodically. Signed-off-by: Ganapatrao Kulkarni --- drivers/perf/Kconfig | 9 + drivers

[PATCH v7 2/2] ThunderX2, perf : Add Cavium ThunderX2 SoC UNCORE PMU driver

This patch adds a perf driver for the PMU UNCORE devices DDR4 Memory Controller(DMC) and Level 3 Cache(L3C). Each PMU supports up to 4 counters. All counters lack overflow interrupt and are sampled periodically. Signed-off-by: Ganapatrao Kulkarni --- drivers/perf/Kconfig | 9 + drivers

[PATCH v7 0/2] Add ThunderX2 SoC Performance Monitoring Unit driver

This patchset adds PMU driver for Cavium's ThunderX2 SoC UNCORE devices. The SoC has PMU support in L3 cache controller (L3C) and in the DDR4 Memory Controller (DMC). v7: Incorporated review comments [3]. Modified driver as loadable module. Updated Documentation with Event

[PATCH v7 1/2] perf, uncore: Adding documentation for ThunderX2 pmu uncore driver

The SoC has PMU support in its L3 cache controller (L3C) and in the DDR4 Memory Controller (DMC). Signed-off-by: Ganapatrao Kulkarni --- Documentation/perf/thunderx2-pmu.txt | 106 +++ 1 file changed, 106 insertions(+) create mode 100644 Documentation/perf/thunderx2-pmu.