Hi Christoph,
Às 7:14 PM de 3/8/2017, Christoph Hellwig escreveu:
> On Wed, Mar 08, 2017 at 03:32:03PM +0000, Joao Pinto wrote:
>> #define PCIE_GET_ATU_INB_UNR_REG_ADDR(region, register) \
>> ((0x3 <&l
Às 1:31 PM de 3/8/2017, Kishon Vijay Abraham I escreveu:
> Hi,
>
> On Wednesday 08 March 2017 05:07 PM, Joao Pinto wrote:
>> Às 11:35 AM de 3/8/2017, Kishon Vijay Abraham I escreveu:
>>> Hi,
>>>
>>> On Wednesday 08 March 2017 05:02 PM, Joao Pinto wrote
Às 3:32 PM de 3/8/2017, Joao Pinto escreveu:
> Às 1:31 PM de 3/8/2017, Kishon Vijay Abraham I escreveu:
>> Hi,
>>
>> On Wednesday 08 March 2017 05:07 PM, Joao Pinto wrote:
>>> Às 11:35 AM de 3/8/2017, Kishon Vijay Abraham I escreveu:
>>>> Hi,
>>&
Às 11:35 AM de 3/8/2017, Kishon Vijay Abraham I escreveu:
> Hi,
>
> On Wednesday 08 March 2017 05:02 PM, Joao Pinto wrote:
>>
>> Hi Kishon,
>>
>>>> Can you provide PCIE_GET_ATU_INB_UNR_REG_OFFSET (similar to
>>>> PCIE_GET_ATU_OUTB_UNR_REG_
Hi Kishon,
>> Can you provide PCIE_GET_ATU_INB_UNR_REG_OFFSET (similar to
>> PCIE_GET_ATU_OUTB_UNR_REG_OFFSET)?
>
> Yes of course, I will send you the definition soon.
As promissed here is the definition for Inbound:
+/* register address builder */
+#define PCIE_GET_ATU_INB_UNR_REG_ADDR(region
Hi Kishon,
Às 5:18 AM de 3/7/2017, Kishon Vijay Abraham I escreveu:
> Hi Joao,
>
> On Friday 17 February 2017 10:50 PM, Joao Pinto wrote:
>> Às 9:50 AM de 2/17/2017, Kishon Vijay Abraham I escreveu:
>>> Add endpoint mode support to designware driver. This uses the
>
Às 9:50 AM de 2/17/2017, Kishon Vijay Abraham I escreveu:
> Add endpoint mode support to designware driver. This uses the
> EP Core layer introduced recently to add endpoint mode support.
> *Any* function driver can now use this designware device
> in order to achieve the EP functionality.
>
> Sig
| vendorid
> +| deviceid
> +| revid
> +| progif_code
> +| subclass_code
> +| baseclass_code
> +| cache_line_size
> +| subsys_vendor_id
> +| subsys_id
> +| interrupt_pin
> +
> +The following en
Às 11:37 AM de 2/17/2017, Kishon Vijay Abraham I escreveu:
> Hi Joao,
>
> On Friday 17 February 2017 04:56 PM, Joao Pinto wrote:
>>
>> Hi Kishon,
>>
>> Às 9:50 AM de 2/17/2017, Kishon Vijay Abraham I escreveu:
>>> Introduce a new EP core layer in order
tion to the host.
> +
> +2.2.2 Other APIs
> +There are other APIs provided by the EPF library. These are used to notify
> +the function driver when the EPF device is bound to the EPC device.
> +pci-ep-cfs.c can be used as reference for using these APIs.
> +
> +*) pci_epf
Hi Kishon,
Às 9:50 AM de 2/17/2017, Kishon Vijay Abraham I escreveu:
> Introduce a new EP core layer in order to support endpoint functions
> in linux kernel. This comprises of EPC library
> (Endpoint Controller Library) and EPF library (Endpoint
> Function Library). EPC library implements functi
Às 11:30 AM de 1/16/2017, Kishon Vijay Abraham I escreveu:
> Hi Joao,
>
> On Monday 16 January 2017 03:57 PM, Joao Pinto wrote:
>>
>> Hi,
>>
>> Às 5:21 AM de 1/16/2017, Kishon Vijay Abraham I escreveu:
>>> Hi Joao,
>>>
>>> On Friday 13
Hi,
Às 5:21 AM de 1/16/2017, Kishon Vijay Abraham I escreveu:
> Hi Joao,
>
> On Friday 13 January 2017 10:19 PM, Joao Pinto wrote:
>> Às 10:26 AM de 1/12/2017, Kishon Vijay Abraham I escreveu:
>>> Split pcie-designware.c into pcie-designware-host.c that contains
>&g
Hi,
Às 5:19 AM de 1/16/2017, Kishon Vijay Abraham I escreveu:
> Hi,
>
> On Friday 13 January 2017 10:43 PM, Joao Pinto wrote:
>> Hi,
>>
>> Às 10:25 AM de 1/12/2017, Kishon Vijay Abraham I escreveu:
>>> *num-lanes* dt property is parsed in dw_pcie_host_init.
Hi Kishon,
Às 10:26 AM de 1/12/2017, Kishon Vijay Abraham I escreveu:
> Now that pci designware host has a separate file, create a new
> config symbol to select the host only driver. This is in preparation
> to enable endpoint support to designware driver.
>
> Signed-off-by: Kishon Vijay Abraham
Hi,
Às 10:25 AM de 1/12/2017, Kishon Vijay Abraham I escreveu:
> *num-lanes* dt property is parsed in dw_pcie_host_init. However
> *num-lanes* property is applicable to both root complex mode and
> endpoint mode. As a first step, move the parsing of this property
> outside dw_pcie_host_init. This
Hi!
Às 10:25 AM de 1/12/2017, Kishon Vijay Abraham I escreveu:
> No functional change. Get device pointer at the beginning of
> dw_pcie_host_init instead of getting it all over dw_pcie_host_init.
> This is in preparation for splitting struct pcie_port into host and
> core structures (Once split p
ichard Zhu
> Cc: Lucas Stach
> Cc: Murali Karicheri
> Cc: Minghuan Lian
> Cc: Mingkai Hu
> Cc: Roy Zang
> Cc: Thomas Petazzoni
> Cc: Niklas Cassel
> Cc: Jesper Nilsson
> Cc: Joao Pinto
> Cc: Zhou Wang
> Cc: Gabriele Paoloni
> Cc: Stanimir
Às 10:26 AM de 1/12/2017, Kishon Vijay Abraham I escreveu:
> Split pcie-designware.c into pcie-designware-host.c that contains
> the host specific parts of the driver and pcie-designware.c that
> contains the parts used by both host driver and endpoint driver.
>
> Signed-off-by: Kishon Vijay Abrah
u32 devfn, int where, int size, u32 val)
> {
> int ret, type;
> u32 busdev, cfg_size;
> @@ -711,7 +711,7 @@ static int dw_pcie_valid_device(struct pcie_port *pp,
> struct pci_bus *bus,
> }
>
> static int dw_pcie_rd_conf(struct pci_bus *bus, u32 devfn, in
.
> This is in preparation for added endpoint support to linux kernel.
>
> Cc: Jingoo Han
> Cc: Murali Karicheri
> Cc: Joao Pinto
> Cc: Stanimir Varbanov
> Cc: Pratyush Anand
> Signed-off-by: Kishon Vijay Abraham I
> ---
> drivers/pci/dwc/pci-dra7xx.c |
gt; };
>
> struct pcie_host_ops {
> + u64 (*cpu_addr_fixup)(u64 cpu_addr);
> u32 (*readl_rc)(struct pcie_port *pp, u32 reg);
> void (*writel_rc)(struct pcie_port *pp, u32 reg, u32 val);
> int (*rd_own_conf)(struct pcie_port *pp, int where, int size
gt;
> #include "pcie-designware.h"
Make sense.
Reviewed-By: Joao Pinto
--
To unsubscribe from this list: send the line "unsubscribe linux-doc" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
23 matches
Mail list logo
