Re: [PATCH 1/4] arm64: add support for the AMU extension v1

Hi Catalin, On 10/10/2019 18:20, Catalin Marinas wrote: > Hi Ionela, > > On Tue, Sep 17, 2019 at 02:42:25PM +0100, Ionela Voinescu wrote: >> +#ifdef CONFIG_ARM64_AMU_EXTN >> + >> +/* >> + * This per cpu variable only signals that the CPU implementation support

[PATCH 4/4] Documentation: arm64: document support for the AMU extension

userspace Signed-off-by: Ionela Voinescu Cc: Catalin Marinas Cc: Will Deacon Cc: Jonathan Corbet --- Documentation/arm64/amu.rst | 107 ++ Documentation/arm64/booting.rst | 14 +++ Documentation/arm64/cpu-feature-registers.rst | 2

[PATCH 1/4] arm64: add support for the AMU extension v1

interface for AMU aarch64 registers - (while here) create defines for ID_PFR0_EL1 fields when adding the AMU field information. Signed-off-by: Ionela Voinescu Cc: Catalin Marinas Cc: Will Deacon Cc: Suzuki K Poulose Cc: Marc Zyngier Cc: Mark Rutland --- arch/arm64/Kconfig | 27

[PATCH 2/4] arm64: trap to EL1 accesses to AMU counters from EL0

, disable direct accesses to activity monitors counters from EL0 (userspace) and trap them to EL1 (kernel). Signed-off-by: Ionela Voinescu Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Rutland Cc: Steve Capper --- arch/arm64/include/asm/assembler.h | 10 ++ arch/arm64/mm/proc.S

[PATCH 3/4] arm64/kvm: disable access to AMU registers from kvm guests

feature register (SYS_ID_AA64PFR0_EL1 and SYS_ID_PFR0_EL1) on the VCPU. - Disabling access to the AMU registers before switching to the guest. - Trapping accesses and injecting an undefined instruction into the guest. Signed-off-by: Ionela Voinescu Cc: Marc Zyngier Cc: James Morse Cc: Julien

[PATCH 0/4] arm64: ARMv8.4 Activity Monitors support

m FVP: Architecture Envelope Model [1] (supports version 8.0 to 8.5), with the following configurations: cluster0.has_arm_v8-4=1 cluster1.has_arm_v8-4=1 cluster0.has_amu=1 cluster1.has_amu=1 [1] https://developer.arm.com/tools-and-software/simulation-models/fixed-virtual-platforms I