0_socdk_sdmmc.dts | 12
> 1 file changed, 12 insertions(+)
>
Acked-by: Dinh Nguyen
Thanks,
Dinh
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<42 IRQ_TYPE_LEVEL_HIGH>;
> + };
> };
>
> rst: rstmgr@ffd05000 {
>
Acked-by: Dinh Nguyen
Dinh
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<34 IRQ_TYPE_LEVEL_HIGH>;
> + };
> };
>
> rst: rstmgr@ffd05000 {
>
Acked-by: Dinh Nguyen
Dinh
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On 06/27/2016 11:18 AM, Borislav Petkov wrote:
> On Mon, Jun 27, 2016 at 10:31:29AM -0500, Dinh Nguyen wrote:
>> I've applied this patch and will take through the arm-soc tree.
>
> I already took the whole branch two days ago:
>
> http://git.kernel.org/cgit/linux/kerne
Hi Boris,
On 06/22/2016 08:58 AM, ttha...@opensource.altera.com wrote:
> From: Thor Thayer
>
> Add the device tree entries needed to support the Altera Ethernet
> FIFO buffer EDAC on the Arria10 chip.
>
> Signed-off-by: Thor Thayer
> ---
> v2 No change
> v3 Add interrupts for SBERR and DBERR
On Wed, 25 May 2016, ttha...@opensource.altera.com wrote:
> From: Thor Thayer
>
> Changes to support IRQ controller implementation including adding
> new property irq-controller to eccmgr and adding IRQ property
> to children.
>
> Signed-off-by: Thor Thayer
> ---
> arch/arm/boot/dts/socfpga_a
On Wed, 25 May 2016, ttha...@opensource.altera.com wrote:
> From: Thor Thayer
>
> Changes to support ECC Manager as SDRAM IRQ parent by
> 1) updating IRQ property values to correct child IRQs
> 2) moving node under ECC Manager.
>
> Signed-off-by: Thor Thayer
> ---
> arch/arm/boot/dts/socfpga_
On Thu, 31 Mar 2016, ttha...@opensource.altera.com wrote:
> From: Thor Thayer
>
> Add the device tree entries needed to support the Altera On-Chip
> RAM EDAC on the Arria10 chip.
>
> Signed-off-by: Thor Thayer
> ---
> v2: No change
> ---
> arch/arm/boot/dts/socfpga_arria10.dtsi |5 +
>
es. Because I've applied 1-4 already.
>
> Yes, no?
>
> If no, then please send only an updated version of this patch as a reply
> to this thread here.
>
My only suggestion was to change the 3 helper functions(ecc_set_bits,
ecc_clear_bits, and ecc_test_bits) should be stati
On Wed, 30 Mar 2016, ttha...@opensource.altera.com wrote:
> From: Thor Thayer
>
> Enable ECC for Arria10 On-Chip RAM on machine startup. The ECC has to be
> enabled before data is stored in memory otherwise the ECC will fail
> on reads.
>
> Signed-off-by: Thor Thayer
> ---
[snip]
> +
> +void
On Tue, Mar 29, 2016 at 9:00 AM, Borislav Petkov wrote:
> Fine with me as long as people don't start complaining if they start
> testing my for-next branch and realize that the Arria10 support is not
> complete.
>
> Unless they test linux-next where your tree is too, I assume.
>
Yes, I take the p
Hi Boris,
On Tue, Mar 29, 2016 at 3:45 AM, Borislav Petkov wrote:
> On Mon, Mar 21, 2016 at 11:01:46AM -0500, ttha...@opensource.altera.com wrote:
>> From: Thor Thayer
>>
>> Add the device tree entries needed to support the Altera L2
>> cache EDAC on the Arria10 chip.
>>
>> Signed-off-by: Thor
On 03/07/2016 01:43 PM, ttha...@opensource.altera.com wrote:
> From: Thor Thayer
>
> Add the device tree entries needed to support the Altera L2
> cache EDAC on the Arria10 chip.
>
> Signed-off-by: Thor Thayer
> ---
> v2 Match register value (l2-ecc@ffd06010)
> ---
> arch/arm/boot/dts/socfpg
socfpga/socfpga.c | 10 +++-
> 3 files changed, 59 insertions(+), 1 deletion(-)
>
Acked-by: Dinh Nguyen
Thanks,
Dinh
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On Tue, 1 Mar 2016, ttha...@opensource.altera.com wrote:
> From: Thor Thayer
>
> Enable ECC for Arria10 L2 cache on machine startup. The ECC has to be
> enabled before data is stored in memory otherwise the ECC will fail
> on reads.
>
> Signed-off-by: Thor Thayer
> ---
> arch/arm/mach-socfpga
+
> arch/arm/mach-socfpga/socfpga.c |3 +++
> 4 files changed, 54 insertions(+)
> create mode 100644 arch/arm/mach-socfpga/ocram.c
>
Acked-by: Dinh Nguyen
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r in header.
> ---
> arch/arm/mach-socfpga/Makefile |1 +
> arch/arm/mach-socfpga/core.h |1 +
> arch/arm/mach-socfpga/l2_cache.c | 41
> ++
> arch/arm/mach-socfpga/socfpga.c |2 ++
> 4 files changed, 45 insertions(+)
> cre
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