Documentation for perf usage and Hisilicon SoC PMU uncore events.
The Hisilicon SOC has event counters for hardware modules like
L3 cache, Miscellaneous node etc. These events are all uncore.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
---
Documentation/perf/hisi-pmu.txt | 75
Thanks for the review.
On Tuesday 21 March 2017 07:42 PM, Mark Rutland wrote:
Hi,
On Fri, Mar 10, 2017 at 01:27:39AM -0500, Anurup M wrote:
+HiP0x chips are encapsulated by multiple CPU and IO die's. The CPU die is
Nit: that apostrophe shouldn't be there.
Ok. shall recheck
Documentation for perf usage and Hisilicon SoC PMU uncore events.
The Hisilicon SOC has event counters for hardware modules like
L3 cache, Miscellaneous node etc. These events are all uncore.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
---
Documentation/perf/hisi-pmu.txt | 76
Documentation for perf usage and Hisilicon SoC PMU uncore events.
The Hisilicon SOC has event counters for hardware modules like
L3 cache, Miscellaneous node etc. These events are all uncore.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
---
Documentation/perf/hisi-pmu.txt | 76
On Tuesday 10 January 2017 11:25 PM, Mark Rutland wrote:
On Mon, Jan 02, 2017 at 01:49:37AM -0500, Anurup M wrote:
+The Hisilicon SoC HiP05/06/07 chips consist of various independent system
+device PMU's such as L3 cache(L3C) and Miscellaneous Nodes(MN).
+These PMU devices are independen
Documentation for perf usage and Hisilicon SoC PMU uncore events.
The Hisilicon SOC has event counters for hardware modules like
L3 cache, Miscellaneous node etc. These events are all uncore.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
---
Documentation/perf/hisi-pmu.txt | 75
Documentation for perf usage and Hisilicon SoC PMU uncore events.
The Hisilicon SOC has event counters for hardware modules like
L3 cache, Miscellaneous node etc. These events are all uncore.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
---
Documentation/perf/hisi-pmu.txt | 75
On Tuesday 15 November 2016 03:21 PM, Mark Rutland wrote:
On Mon, Nov 14, 2016 at 05:36:44AM +0530, Anurup M wrote:
On Friday 11 November 2016 12:00 AM, Mark Rutland wrote:
On Thu, Nov 03, 2016 at 01:42:01AM -0400, Anurup M wrote:
+ - scl-id : The Super Cluster ID. This can be the ID
On Thursday 10 November 2016 11:25 PM, Mark Rutland wrote:
On Thu, Nov 03, 2016 at 01:41:59AM -0400, Anurup M wrote:
From: Tan Xiaojun
The Hisilicon Djtag is an independent component which connects
with some other components in the SoC by Debug Bus. This driver
can
On Friday 11 November 2016 12:40 AM, Mark Rutland wrote:
On Thu, Nov 03, 2016 at 01:42:03AM -0400, Anurup M wrote:
+ do {
+ /* Get count from individual L3C banks and sum them up */
+ for (i = 0; i < num_banks; i++) {
+ total_raw_co
On Friday 11 November 2016 12:00 AM, Mark Rutland wrote:
Hi,
On Thu, Nov 03, 2016 at 01:42:01AM -0400, Anurup M wrote:
1) Device tree bindings for Hisilicon SoC PMU.
2) Add example for Hisilicon L3 cache, MN and DDRC PMU.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
On Friday 11 November 2016 05:23 PM, Mark Rutland wrote:
On Fri, Nov 11, 2016 at 04:49:03PM +0530, Anurup M wrote:
On Thursday 10 November 2016 10:53 PM, Mark Rutland wrote:
On Thu, Nov 03, 2016 at 01:41:58AM -0400, Anurup M wrote:
diff --git a/Documentation/devicetree/bindings/arm
On Thursday 10 November 2016 10:53 PM, Mark Rutland wrote:
Hi,
On Thu, Nov 03, 2016 at 01:41:58AM -0400, Anurup M wrote:
From: Tan Xiaojun
1) Add Hisilicon HiP05/06/07 CPU and ALGSUB system controller dts
bindings.
2) Add Hisilicon Djtag dts binding.
Signed-off
On Thursday 03 November 2016 11:56 PM, Krzysztof Kozlowski wrote:
On Thu, Nov 03, 2016 at 01:42:01AM -0400, Anurup M wrote:
1) Device tree bindings for Hisilicon SoC PMU.
2) Add example for Hisilicon L3 cache, MN and DDRC PMU.
Get rid of this weird indentation in all patches
1. Add support for counting Hisilicon DDRC
statistics events in perf.
2. Support a total of 13 statistics events.
3. Events listed in /sys/devices//
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
---
drivers/perf/hisilicon/Makefile | 2
attribute group for showing the available CPU
for counting.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
---
drivers/perf/hisilicon/hisi_uncore_l3c.c | 57
drivers/perf/hisilicon/hisi_uncore_pmu.c | 40 ++
drivers/perf
1. Add nodes for hip06 L3 cache to support uncore events.
2. Add nodes for hip06 MN to support uncore events.
3. Add nodes for hip06 DDRC to support uncore events.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
Signed-off-by: John Garry
---
arch/arm64/boot/dts
event format is
-e "hisi_mn2/read_req/"
Signed-off-by: Shaokun Zhang
Signed-off-by: Anurup M
---
drivers/perf/hisilicon/Makefile | 2 +-
drivers/perf/hisilicon/hisi_uncore_mn.c | 571
drivers/perf/hisilicon/hisi_uncore_mn.h |
-off-by: Tan Xiaojun
Signed-off-by: John Garry
Signed-off-by: Anurup M
---
drivers/soc/Kconfig | 1 +
drivers/soc/Makefile| 1 +
drivers/soc/hisilicon/Kconfig | 12 +
drivers/soc/hisilicon/Makefile | 1 +
drivers/soc/hisilicon/djtag.c | 639
Documentation for perf usage and Hisilicon SoC PMU uncore events.
The Hisilicon SOC has event counters for hardware modules like
L3 cache, Miscellaneous node, DDR cntroller etc. These events are
all uncore.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
. Routines to enable/disable/add/del/start/stop hardware
event counting.
5. Add support to count L3 cache hardware events.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
Signed-off-by: John Garry
---
drivers/perf/Makefile| 1 +
drivers/perf
1) Device tree bindings for Hisilicon SoC PMU.
2) Add example for Hisilicon L3 cache, MN and DDRC PMU.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
---
.../devicetree/bindings/arm/hisilicon/pmu.txt | 127 +
1 file changed, 127 insertions
From: Tan Xiaojun
1) Add Hisilicon HiP05/06/07 CPU and ALGSUB system controller dts
bindings.
2) Add Hisilicon Djtag dts binding.
Signed-off-by: Tan Xiaojun
Signed-off-by: Anurup M
---
.../bindings/arm/hisilicon/hisilicon.txt | 82
1. Update Kconfig for Hip05/06/07 PMU support.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
Signed-off-by: John Garry
---
drivers/perf/Kconfig | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/perf/Kconfig b/drivers/perf/Kconfig
index 4d5c5f9..da8dd97 100644
Add support for Hisilicon SoC hardware event counters
for HIP05/06/07 chip versions.
Signed-off-by: Anurup M
---
MAINTAINERS | 10 ++
1 file changed, 10 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index b224caa..839abc8 100644
--- a/MAINTAINERS
+++ b
corresponding events files
under the PMU directory so the perf tool can list the event names.
ToDo:
1) The counter overflow handling is currently unsupported in this
patch series.
2) ACPI support.
Anurup M (8):
arm64: MAINTAINERS: hisi: Add hisilicon SoC PMU support
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