Re: [PATCH v5 0/2] perf: riscv: Preliminary Perf Event Support on RISC-V

12:27:26 PDT (-0700), atish.pa...@wdc.com wrote: > >>>>On 4/24/18 11:07 AM, Atish Patra wrote: > >>>>>On 4/19/18 4:28 PM, Alan Kao wrote: > >>>>>However, I got an rcu-stall for the test "47: Event times". > >>>>># ./

[PATCH v5 1/2] perf: riscv: preliminary RISC-V support

-Spec. Note that the latest qemu model hasn't fully support a proper behavior of Priv-Spec 1.10 yet, but work around should be easy with very small fixes. Please check https://github.com/riscv/riscv-qemu/pull/115 for future updates. Cc: Nick Hu Cc: Greentime Hu Signed-off-by: Alan Kao ---

[PATCH v5 2/2] perf: riscv: Add Document for Future Porting Guide

Reviewed-by: Alex Solomatnikov Cc: Nick Hu Cc: Greentime Hu Signed-off-by: Alan Kao --- Documentation/riscv/pmu.txt | 249 1 file changed, 249 insertions(+) create mode 100644 Documentation/riscv/pmu.txt diff --git a/Documentation/riscv/pmu.txt b

[PATCH v5 0/2] perf: riscv: Preliminary Perf Event Support on RISC-V

, which was caused by not sufficient initialization. Check https://lkml.org/lkml/2018/3/31/251 for the discussion. Alan Kao (2): perf: riscv: preliminary RISC-V support perf: riscv: Add Document for Future Porting Guide Documentation/riscv/pmu.txt | 249 ++ arch/riscv

Re: [PATCH v4 1/2] perf: riscv: preliminary RISC-V support

On Thu, Apr 19, 2018 at 12:46:24PM -0700, Atish Patra wrote: > On 4/17/18 7:13 PM, Alan Kao wrote: > >This patch provide a basic PMU, riscv_base_pmu, which supports two > >general hardware event, instructions and cycles. Furthermore, this > >PMU serves as a reference imple

[PATCH v4 2/2] perf: riscv: Add Document for Future Porting Guide

Reviewed-by: Alex Solomatnikov Cc: Nick Hu Cc: Greentime Hu Signed-off-by: Alan Kao --- Documentation/riscv/pmu.txt | 249 1 file changed, 249 insertions(+) create mode 100644 Documentation/riscv/pmu.txt diff --git a/Documentation/riscv/pmu.txt b

[PATCH v4 1/2] perf: riscv: preliminary RISC-V support

-Spec. Note that the latest qemu model hasn't fully support a proper behavior of Priv-Spec 1.10 yet, but work around should be easy with very small fixes. Please check https://github.com/riscv/riscv-qemu/pull/115 for future updates. Cc: Nick Hu Cc: Greentime Hu Signed-off-by: Alan Kao ---

[PATCH v4 0/2] perf: riscv: Preliminary Perf Event Support on RISC-V

https://lkml.org/lkml/2018/3/31/251 for the discussion. Alan Kao (2): perf: riscv: preliminary RISC-V support perf: riscv: Add Document for Future Porting Guide Documentation/riscv/pmu.txt | 249 ++ arch/riscv/Kconfig | 13 + arch/riscv/include/asm

[PATCH v3 2/2] perf: riscv: Add Document for Future Porting Guide

Reviewed-by: Alex Solomatnikov Cc: Nick Hu Cc: Greentime Hu Signed-off-by: Alan Kao --- Documentation/riscv/pmu.txt | 249 1 file changed, 249 insertions(+) create mode 100644 Documentation/riscv/pmu.txt diff --git a/Documentation/riscv/pmu.txt b

[PATCH v3 0/2] perf: riscv: Preliminary Perf Event Support on RISC-V

device-tree-based methods, and set default to the PMU proposed in this patch. Changes in v2: - Fix the bug reported by Alex, which was caused by not sufficient initialization. Check https://lkml.org/lkml/2018/3/31/251 for the discussion. Alan Kao (2): perf: riscv: preliminary RISC-V

[PATCH v3 1/2] perf: riscv: preliminary RISC-V support

-Spec. Note that the latest qemu model hasn't fully support a proper behavior of Priv-Spec 1.10 yet, but work around should be easy with very small fixes. Please check https://github.com/riscv/riscv-qemu/pull/115 for future updates. Cc: Nick Hu Cc: Greentime Hu Signed-off-by: Alan Kao ---

Re: [PATCH 1/2] perf: riscv: preliminary RISC-V support

iv-Spec 1.10 yet, but work > >around should be easy with very small fixes. Please check > >https://github.com/riscv/riscv-qemu/pull/115 for future updates. > > > >Cc: Nick Hu > >Cc: Greentime Hu > >Signed-off-by: Alan Kao > > We should really be able

Re: [PATCH v2 2/2] perf: riscv: Add Document for Future Porting Guide

Hi Alex, On Tue, Apr 03, 2018 at 07:08:43PM -0700, Alex Solomatnikov wrote: > Doc fixes: > > Thanks for these fixes. I'll edit this patch and send a v3 once I am done with the PMU patch. I suppose a "Reviewed-by: Alex Solomatnikov" appending at the end of the commit will be great, right? Alan

Re: [PATCH 0/2] perf: riscv: Preliminary Perf Event Support on RISC-V

>>> - Fix the bug reported by Alex, which was caused by not sufficient > >>> initialization. Check https://lkml.org/lkml/2018/3/31/251 for the > >>> discussion. > >>> > >>>Alan Kao (2): > >>> perf: riscv: preliminary RISC-V su

Re: [PATCH v2 0/2] perf: riscv: Preliminary Perf Event Support on RISC-V

Sorry for the lack of version prefix in the title. This patchset should be version 2. On Mon, Apr 02, 2018 at 08:31:22PM +0800, Alan Kao wrote: > This implements the baseline PMU for RISC-V platforms. > > To ease future PMU portings, a guide is also written, containing > perf co

[PATCH v2 2/2] perf: riscv: Add Document for Future Porting Guide

Cc: Nick Hu Cc: Greentime Hu Signed-off-by: Alan Kao --- Documentation/riscv/pmu.txt | 249 1 file changed, 249 insertions(+) create mode 100644 Documentation/riscv/pmu.txt diff --git a/Documentation/riscv/pmu.txt b/Documentation/riscv/pmu.txt new

[PATCH v2 1/2] perf: riscv: preliminary RISC-V support

-Spec. Note that the latest qemu model hasn't fully support a proper behavior of Priv-Spec 1.10 yet, but work around should be easy with very small fixes. Please check https://github.com/riscv/riscv-qemu/pull/115 for future updates. Cc: Nick Hu Cc: Greentime Hu Signed-off-by: Alan Kao ---

[PATCH 0/2] perf: riscv: Preliminary Perf Event Support on RISC-V

://lkml.org/lkml/2018/3/31/251 for the discussion. Alan Kao (2): perf: riscv: preliminary RISC-V support perf: riscv: Add Document for Future Porting Guide Documentation/riscv/pmu.txt | 249 +++ arch/riscv/Kconfig | 12 + arch/riscv/include/asm

Re: [PATCH 1/2] perf: riscv: preliminary RISC-V support

Hi Alex, On Mon, Apr 02, 2018 at 03:36:12PM +0800, Alan Kao wrote: > On Sat, Mar 31, 2018 at 03:47:10PM -0700, Alex Solomatnikov wrote: > > The original guess was that maybe, an counter value on a hart is picked > as the minusend, and an old counter value on another hart was recor

Re: [PATCH 1/2] perf: riscv: preliminary RISC-V support

is first: * What is the frequency of that "funny number" event? Was that often? * If you monitor only one hart, will the event disappear? * What will happen if you change the counter_width to fit U54's counter width? * Is the test program you used open-sourced? > Alex >

Re: [PATCH 1/2] perf: riscv: preliminary RISC-V support

# L1 Instruction 32K [2] > # L1 Data 32K [2] > # L1 Instruction 32K [3] > # L1 Data 32K [3] > # missing features: TRACING_DATA BUILD_ID CPUDESC CPUID NUMA_TOPOLOGY > BRANCH_STACK GROUP_DESC AUXTRACE STAT > # > > >

[PATCH 2/2] perf: riscv: Add Document for Future Porting Guide

Cc: Nick Hu Cc: Greentime Hu Signed-off-by: Alan Kao --- Documentation/riscv/pmu.txt | 250 1 file changed, 250 insertions(+) create mode 100644 Documentation/riscv/pmu.txt diff --git a/Documentation/riscv/pmu.txt b/Documentation/riscv/pmu.txt new

[PATCH 0/2] perf: riscv: Preliminary Perf Event Support on RISC-V

This implements the baseline PMU for RISC-V platforms. To ease the future PMU portings, a guide is also written, containing perf concepts, arch porting practices and some hints. Alan Kao (2): perf: riscv: preliminary RISC-V support perf: riscv: Add Document for Future Porting Guide

[PATCH 1/2] perf: riscv: preliminary RISC-V support

-Spec. Note that the latest qemu model hasn't fully support a proper behavior of Priv-Spec 1.10 yet, but work around should be easy with very small fixes. Please check https://github.com/riscv/riscv-qemu/pull/115 for future updates. Cc: Nick Hu Cc: Greentime Hu Signed-off-by: Alan Kao ---