On 2/11/2025 9:55 PM, Andrew Lunn wrote:
+#define PRINT_COUNTER_PREFIX(desc, cnt_type) \
+ seq_printf(seq, "%-16s %16s", desc, cnt_type)
+
+#define PRINT_CPU_CODE_COUNTER(cnt, code) \
+ seq_printf(seq, "%10u(cpucode:%d)", cnt, code)
+
+#define PRINT_DROP_CODE
On 2/12/2025 9:58 AM, Jie Gan wrote:
+static int qcom_ppe_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct ppe_device *ppe_dev;
+ void __iomem *base;
+ int ret, num_icc;
I think it's better with:
int num_icc = ARRAY_SIZE(ppe_icc_data);
This
Hi Mauro,
On 2/13/25 4:06 AM, Mauro Carvalho Chehab wrote:
> Hi Jon,
>
> That's the second version of the Python kernel-doc tool.
>
> As the previous version, I tried to stay as close as possible of the original
> Perl implementation, as it helps to double check if each function was
> properly
In order to simplify interdependencies in the rest of the series define
the feature detection for SME and it's subfeatures. Due to the need for
vector length configuration we define a flag for SME like for SVE. We
also have two subfeatures which add architectural state, FA64 and SME2,
which are c
The primary register for identifying SME is ID_AA64PFR1_EL1.SME. This
is hidden from guests unless SME is enabled by the VMM.
When it is visible it is writable and can be used to control the
availability of SME2.
There is also a new register ID_AA64SMFR0_EL1 which we make writable,
forcing it to
SME has optional support for configuring the relative priorities of PEs
in systems where they share a single SME hardware block, known as a
SMCU. Currently we do not have any support for this in Linux and will
also hide it from KVM guests, pending experience with practical
implementations. The inte
Add coverage of the SME ID registers to set_id_regs, ID_AA64PFR1_EL1.SME
becomes writable and we add ID_AA64SMFR_EL1 and it's subfields.
Signed-off-by: Mark Brown
---
tools/testing/selftests/kvm/arm64/set_id_regs.c | 29 +++--
1 file changed, 27 insertions(+), 2 deletions(-)
Since SME requires configuration of a vector length in order to know the
size of both the streaming mode SVE state and ZA array we implement a
capability for it and require that it be enabled and finalized before
the SME specific state can be accessed, similarly to SVE.
Due to the overlap with siz
SME adds a number of new system registers, update get-reg-list to check for
them based on the visibility of SME.
Signed-off-by: Mark Brown
---
tools/testing/selftests/kvm/arm64/get-reg-list.c | 32 +++-
1 file changed, 31 insertions(+), 1 deletion(-)
diff --git a/tools/testi
With support for context switching SME state in place allow access to SME
in nested guests.
The SME floating point state is handled along with all the other floating
point state, SME specific floating point exceptions are directed into the
same handlers as other floating point exceptions with NV s
The access control for SME follows the same structure as for the base FP
and SVE extensions, with control being via CPACR_ELx.SMEN and CPTR_EL2.TSM
mirroring the equivalent FPSIMD and SVE controls in those registers. Add
handling for these controls and exceptions mirroring the existing handling
for
If the guest has SME state we need to context switch that state, provide
support for that for normal guests.
SME has three sets of registers, ZA, ZT (only present for SME2) and also
streaming SVE which replaces the standard floating point registers when
active. The first two are fairly straightfor
SME introduces two new registers, the ZA matrix register and the ZT0 LUT
register. Both of these registers are only accessible when PSTATE.ZA is
set and ZT0 is only present if SME2 is enabled for the guest. Provide
support for configuring these from VMMs.
The ZA matrix is a single SVL*SVL registe
SME introduces a mode called streaming mode where the Z, P and optionally
FFR registers can be accessed using the SVE instructions but with the SME
vector length. Reflect this in the ABI for accessing the guest registers by
making the vector length for the vcpu reflect the vector length that would
Provide a __sme_restore_state() for the hypervisor to allow it to restore
ZA and ZT for guests.
Signed-off-by: Mark Brown
---
arch/arm64/include/asm/kvm_hyp.h | 2 ++
arch/arm64/kvm/hyp/fpsimd.S | 16
2 files changed, 18 insertions(+)
diff --git a/arch/arm64/include/asm/k
SME adds a new thread ID register, TPIDR2_EL0. This is used in userspace
for delayed saving of the ZA state but in terms of the architecture is
not really connected to SME other than being part of FEAT_SME. It has an
independent fine grained trap and the runtime connection with the rest
of SME is p
SME adds a second vector length configured in a very similar way to the
SVE vector length, in order to facilitate future code sharing for SME
refactor our storage of vector lengths to use an array like the host does.
We do not yet take much advantage of this so the intermediate code is not
as clean
SME implements a vector length which architecturally looks very similar
to that for SVE, configured in a very similar manner. This controls the
vector length used for the ZA matrix register, and for the SVE vector
and predicate registers when in streaming mode. The only substantial
difference is
SME is configured by the system registers SMCR_EL1 and SMCR_EL2, add
definitions and userspace access for them. These control the SME vector
length in a manner similar to that for SVE and also have feature enable
bits for SME2 and FA64. A subsequent patch will add management of them
for guests as
SME, the Scalable Matrix Extension, is an arm64 extension which adds
support for matrix operations, with core concepts patterned after SVE.
SVE introduced some complication in the ABI since it adds new vector
floating point registers with runtime configurable size, the size being
controlled by a p
As for SVE we will need to pull parts of dynamically sized registers out of
a block of memory for SME so we will use a similar code pattern for this.
Rename the current struct sve_state_reg_region in preparation for this.
No functional change.
Signed-off-by: Mark Brown
---
arch/arm64/kvm/guest.
In preparation for SME support move the macros used to access SVE state
after the feature test macros, we will need to test for SME subfeatures to
determine the size of the SME state.
Signed-off-by: Mark Brown
---
arch/arm64/include/asm/kvm_host.h | 46 +++
1
Due to the overlap between SVE and SME vector length configuration
created by streaming mode SVE we will finalize both at once. Rename the
existing finalization to use _VEC (vector) for the naming to avoid
confusion.
Since this includes the userspace API we create an alias
KVM_ARM_VCPU_VEC for th
Rather than add earlier prototypes of specific ctxt_has_ helpers let's just
pull all their definitions to the top of sysreg-sr.h so they're all
available to all the individual save/restore functions.
Signed-off-by: Mark Brown
---
arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h | 62 +++---
The hypervisor copies of the SVE save and load functions are prototyped
with third arguments specifying FFR should be accessed but the assembly
functions overwrite whatever is supplied to unconditionally access FFR.
Remove this and use the supplied parameter.
This has no effect currently since FFR
We have support for determining a set of fine grained traps to enable for
the guest which is tied to the support for injecting UNDEFs for undefined
features. This means that we can't use the mechanism for system registers
which should be present but need emulation, such as SMPRI_EL1 which should
be
Currently when deciding if we need to save FFR when in streaming mode prior
to EFI calls we check if FA64 is supported by the system. Since KVM guest
support will mean that FA64 might be enabled and disabled at runtime switch
to checking if traps for FA64 are enabled in SMCR_EL1 instead.
Signed-of
As with SVE we can only virtualise SME vector lengths that are supported by
all CPUs in the system, implement similar checks to those for SVE. Since
unlike SVE there are no specific vector lengths that are architecturally
required the handling is subtly different, we report a system where this
happ
Some parts of the SME state are optional, enabled by additional features
on top of the base FEAT_SME and controlled with enable bits in SMCR_ELx. We
unconditionally enable these for the host but for KVM we will allow the
feature set exposed to guests to be restricted by the VMM. These are the
FFR r
Currently we enable EL0 and EL1 access to FA64 and ZT0 at boot and leave
them enabled throughout the runtime of the system. When we add KVM support
we will need to make this configuration dynamic, these features may be
disabled for some KVM guests. Since the host kernel saves the floating
point sta
I've removed the RFC tag from this version of the series, but the items
that I'm looking for feedback on remains the same:
- The userspace ABI, in particular:
- The vector length used for the SVE registers, access to the SVE
registers and access to ZA and (if available) ZT0 depending on
Mauro Carvalho Chehab writes:
> This series increases the minimal requirements for Sphinx and Python, and
> drop some backward-compatible code from Sphinx extension.
OK, I've gone ahead and applied this series - let's see who screams...
Thanks,
jon
Em Thu, 13 Feb 2025 13:06:17 +0100
Mauro Carvalho Chehab escreveu:
> +def dump_function(self, ln, prototype):
> +
...
> +(r"""
> + __attribute__\s*\(\(
> +(?:
> +[\w\s]++ # attribute name
> +(?:\([^)]*+
On Thu, Feb 13, 2025 at 06:23:55PM +0900, Akihiko Odaki wrote:
> On 2025/02/13 16:18, Michael S. Tsirkin wrote:
> >
> > Commit log needs some work.
> >
> > So my understanding is, this patch does not do much functionally,
> > but makes adding the hash feature easier. OK.
> >
> > On Thu, Feb 13,
On 2/12/25 19:18, Mina Almasry wrote:
On Wed, Feb 12, 2025 at 7:52 AM Pavel Begunkov wrote:
On 2/10/25 21:09, Mina Almasry wrote:
On Wed, Feb 5, 2025 at 4:20 AM Pavel Begunkov wrote:
On 2/3/25 22:39, Mina Almasry wrote:
...
diff --git a/include/linux/skbuff.h b/include/linux/skbuff.h
inde
Maintaining kernel-doc has been a challenge, as there aren't many
perl developers among maintainers. Also, the logic there is too
complex. Having lots of global variables and using pure functions
doesn't help.
Rewrite the script in Python, placing most global variables
inside classes. This should
Hi Jon,
That's the second version of the Python kernel-doc tool.
As the previous version, I tried to stay as close as possible of the original
Perl implementation, as it helps to double check if each function was
properly translated to Python. This have been helpful debugging troubles
that happ
On 2025/02/13 16:18, Michael S. Tsirkin wrote:
Commit log needs some work.
So my understanding is, this patch does not do much functionally,
but makes adding the hash feature easier. OK.
On Thu, Feb 13, 2025 at 03:54:06PM +0900, Akihiko Odaki wrote:
tun used to simply advance iov_iter when it
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