On 07/02/2025 22:26, Deepak Gupta wrote:
> Hi Clement,
>
> Thanks for looking at it. Inline
> On Thu, Feb 06, 2025 at 02:49:09PM +0100, Clément Léger wrote:
>>
>>
>> On 05/02/2025 02:22, Deepak Gupta wrote:
>>> zicfiss / zicfilp introduces a new exception to priv isa `software check
>>> excepti
Em Fri, 7 Feb 2025 12:54:52 +0100
Hans Verkuil escreveu:
> On 09/12/2024 09:15, Mauro Carvalho Chehab wrote:
> > Em Tue, 3 Dec 2024 14:07:12 +0100
> > Mauro Carvalho Chehab escreveu:
> >
> >>
> >> The idea is to gradually open media-committers to more people, as each
> >> phase succeeds, addr
On 2/9/2025 10:29 PM, Luo Jie wrote:
The PPE (packet process engine) hardware block is available in Qualcomm
IPQ chipsets that support PPE architecture, such as IPQ9574. The PPE in
the IPQ9574 SoC includes six ethernet ports (6 GMAC and 6 XGMAC), which
are used to connect with external PHY dev
On Sun, Feb 09, 2025 at 10:29:36PM +0800, Luo Jie wrote:
> +The Ethernet functionality in the PPE (Packet Process Engine) is comprised
> of three
> +components: the switch core, port wrapper and Ethernet DMA.
> +
> +The Switch core in the IPQ9574 PPE has maximum of 6 front panel ports and
> two F
On 2/9/2025 10:29 PM, Luo Jie wrote:
The PPE (Packet Process Engine) hardware block is available
on Qualcomm IPQ SoC that support PPE architecture, such as
IPQ9574.
The PPE in IPQ9574 includes six integrated ethernet MAC
(for 6 PPE ports), buffer management, queue management and
scheduler fun
On Thu, Feb 06, 2025 at 09:50:07PM -0800, Dan Williams wrote:
> Alistair Popple wrote:
> > On Mon, Jan 13, 2025 at 07:35:07PM -0800, Dan Williams wrote:
> > > Alistair Popple wrote:
> >
> > [...]
> >
> > > ...and here is that aformentioned patch:
> >
> > This patch is different from what you ori
QM (queue management) configurations decide the length of PPE
queues and the queue depth for these queues which are used to
drop packets in events of congestion.
There are two types of PPE queues - unicast queues (0-255) and
multicast queues (256-299). These queue types are used to forward
differe
Add maintainer entry for PPE (Packet Process Engine) driver
supported for Qualcomm IPQ SoCs.
Signed-off-by: Luo Jie
---
MAINTAINERS | 8
1 file changed, 8 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 873aa2cce4d7..57c00f9d7753 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@
The PPE hardware counters maintain counters for packets handled by
the various functional blocks of PPE. They help in tracing the packets
passed through PPE and debugging any packet drops.
The counters displayed by this debugfs file are ones that are common
for all Ethernet ports, and they do not
From: Lei Wei
Initialize the L2 bridge settings for the PPE ports to only enable
L2 frame forwarding between CPU port and PPE Ethernet ports.
The per-port L2 bridge settings are initialized as follows:
For PPE CPU port, the PPE bridge TX is enabled and FDB learning is
disabled. For PPE physical
Configure the selected queues to map with an Ethernet DMA ring for the
packet to receive on ARM cores.
As default initialization, all queues assigned to CPU port 0 are mapped
to the EDMA ring 0. This configuration is later updated during Ethernet
DMA initialization.
Signed-off-by: Luo Jie
---
d
1. Enable port specific counters in PPE.
2. Configure the default action as drop when the packet size
is more than the configured MTU of physical port.
Signed-off-by: Luo Jie
---
drivers/net/ethernet/qualcomm/ppe/ppe_config.c | 86 +-
drivers/net/ethernet/qualcomm/ppe/
PPE RSS hash is generated during PPE receive, based on the packet
content (3 tuples or 5 tuples) and as per the configured RSS seed.
The hash is then used to select the queue to transmit the packet
to the ARM CPU.
This patch initializes the RSS hash settings that are used to
generate the hash for
PPE service code is a special code (0-255) that is defined by PPE for
PPE's packet processing stages, as per the network functions required
for the packet.
For packet being sent out by ARM cores on Ethernet ports, The service
code 1 is used as the default service code. This service code is used
to
Configure unicast and multicast hardware queues for the PPE
ports to enable packet forwarding between the ports.
Each PPE port is assigned with a range of queues. The queue ID
selection for a packet is decided by the queue base and queue
offset that is configured based on the internal priority and
The PPE scheduler settings determine the priority of scheduling the
packet across the different hardware queues per PPE port.
Signed-off-by: Luo Jie
---
drivers/net/ethernet/qualcomm/ppe/ppe_config.c | 788 -
drivers/net/ethernet/qualcomm/ppe/ppe_config.h | 37 ++
driver
The BM (Buffer Management) config controls the pause frame generated
on the PPE port. There are maximum 15 BM ports and 4 groups supported,
all BM ports are assigned to group 0 by default. The number of hardware
buffers configured for the port influence the threshold of the flow
control for that po
The PPE (Packet Process Engine) hardware block is available
on Qualcomm IPQ SoC that support PPE architecture, such as
IPQ9574.
The PPE in IPQ9574 includes six integrated ethernet MAC
(for 6 PPE ports), buffer management, queue management and
scheduler functions. The MACs can connect with the exte
From: Lei Wei
Add description and high-level diagram for PPE, driver overview and
module enable/debug information.
Signed-off-by: Lei Wei
Signed-off-by: Luo Jie
---
.../networking/device_drivers/ethernet/index.rst | 1 +
.../device_drivers/ethernet/qualcomm/ppe/ppe.rst | 197 +++
The PPE (packet process engine) hardware block is available in Qualcomm
IPQ chipsets that support PPE architecture, such as IPQ9574. The PPE in
the IPQ9574 SoC includes six ethernet ports (6 GMAC and 6 XGMAC), which
are used to connect with external PHY devices by PCS. It includes an L2
switch func
The PPE (packet process engine) hardware block is available in Qualcomm
IPQ chipsets that support PPE architecture, such as IPQ9574 and IPQ5332.
The PPE in the IPQ9574 SoC includes six ethernet ports (6 GMAC and 6
XGMAC), which are used to connect with external PHY devices by PCS. The
PPE also incl
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