[PATCH v10 12/14] selftests: riscv: Fix vector tests

Overhaul the riscv vector tests to use kselftest_harness to help the test cases correctly report the results and decouple the individual test cases from each other. With this refactoring, only run the test cases if vector is reported and properly report the test case as skipped otherwise. The v_ini

[PATCH v10 14/14] riscv: Add ghostwrite vulnerability

Follow the patterns of the other architectures that use GENERIC_CPU_VULNERABILITIES for riscv to introduce the ghostwrite vulnerability and mitigation. The mitigation is to disable all vector which is accomplished by clearing the bit from the cpufeature field. Ghostwrite only affects thead c9xx CP

[PATCH v10 13/14] selftests: riscv: Support xtheadvector in vector tests

Extend existing vector tests to be compatible with the xtheadvector instructions. Signed-off-by: Charlie Jenkins --- .../selftests/riscv/vector/v_exec_initval_nolibc.c | 23 -- tools/testing/selftests/riscv/vector/v_helpers.c | 17 - tools/testing/selftests/riscv/vector/v_helpers.h |

[PATCH v10 11/14] riscv: hwprobe: Document thead vendor extensions and xtheadvector extension

Document support for thead vendor extensions using the key RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0 and xtheadvector extension using the key RISCV_HWPROBE_VENDOR_EXT_XTHEADVECTOR. Signed-off-by: Charlie Jenkins Reviewed-by: Evan Green --- Documentation/arch/riscv/hwprobe.rst | 10 ++ 1 file

[PATCH v10 10/14] riscv: hwprobe: Add thead vendor extension probing

Add a new hwprobe key "RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0" which allows userspace to probe for the new RISCV_ISA_VENDOR_EXT_XTHEADVECTOR vendor extension. This new key will allow userspace code to probe for which thead vendor extensions are supported. This API is modeled to be consistent with RI

[PATCH v10 09/14] riscv: vector: Support xtheadvector save/restore

Use alternatives to add support for xtheadvector vector save/restore routines. Signed-off-by: Charlie Jenkins Reviewed-by: Conor Dooley --- arch/riscv/include/asm/csr.h | 6 + arch/riscv/include/asm/switch_to.h | 2 +- arch/riscv/include/asm/vector.h| 225 +

[PATCH v10 06/14] RISC-V: define the elements of the VCSR vector CSR

From: Heiko Stuebner The VCSR CSR contains two elements VXRM[2:1] and VXSAT[0]. Define constants for those to access the elements in a readable way. Acked-by: Guo Ren Reviewed-by: Conor Dooley Signed-off-by: Heiko Stuebner Signed-off-by: Charlie Jenkins --- arch/riscv/include/asm/csr.h | 4

[PATCH v10 08/14] riscv: Add xtheadvector instruction definitions

xtheadvector uses different encodings than standard vector for vsetvli and vector loads/stores. Write the instruction formats to be used in assembly code. Co-developed-by: Heiko Stuebner Signed-off-by: Heiko Stuebner Signed-off-by: Charlie Jenkins --- arch/riscv/include/asm/vendor_extensions/t

[PATCH v10 07/14] riscv: csr: Add CSR encodings for CSR_VXRM/CSR_VXSAT

The VXRM vector csr for xtheadvector has an encoding of 0xa and VXSAT has an encoding of 0x9. Co-developed-by: Heiko Stuebner Signed-off-by: Heiko Stuebner Signed-off-by: Charlie Jenkins --- arch/riscv/include/asm/csr.h | 11 --- 1 file changed, 8 insertions(+), 3 deletions(-) diff --

[PATCH v10 05/14] riscv: vector: Use vlenb from DT for thead

If thead,vlenb is provided in the device tree, prefer that over reading the vlenb csr. Signed-off-by: Charlie Jenkins Acked-by: Conor Dooley --- arch/riscv/Kconfig.vendor| 13 +++ arch/riscv/include/asm/cpufeature.h | 2 + arch/riscv/include/asm/vendor_

[PATCH v10 04/14] riscv: Add thead and xtheadvector as a vendor extension

Add support to the kernel for THead vendor extensions with the target of the new extension xtheadvector. Signed-off-by: Charlie Jenkins Reviewed-by: Conor Dooley --- arch/riscv/Kconfig.vendor| 13 + arch/riscv/include/asm/vendor_extensions/thead.h | 16 ++

[PATCH v10 03/14] riscv: dts: allwinner: Add xtheadvector to the D1/D1s devicetree

The D1/D1s SoCs support xtheadvector so it can be included in the devicetree. Also include vlenb for the cpu. Signed-off-by: Charlie Jenkins Reviewed-by: Conor Dooley --- arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/ris

[PATCH v10 02/14] dt-bindings: cpus: add a thead vlen register length property

Add a property analogous to the vlenb CSR so that software can detect the vector length of each CPU prior to it being brought online. Currently software has to assume that the vector length read from the boot CPU applies to all possible CPUs. On T-Head CPUs implementing pre-ratification vector, rea

[PATCH v10 01/14] dt-bindings: riscv: Add xtheadvector ISA extension description

The xtheadvector ISA extension is described on the T-Head extension spec Github page [1] at commit 95358cb2cca9. Link: https://github.com/T-head-Semi/thead-extension-spec/blob/95358cb2cca9489361c61d335e03d3134b14133f/xtheadvector.adoc [1] Signed-off-by: Charlie Jenkins Reviewed-by: Conor Doole

[PATCH v10 00/14] riscv: Add support for xtheadvector

xtheadvector is a custom extension that is based upon riscv vector version 0.7.1 [1]. All of the vector routines have been modified to support this alternative vector version based upon whether xtheadvector was determined to be supported at boot. vlenb is not supported on the existing xtheadvector

Re: [PATCH] kernel-docs: Add new section for Rust learning materials

On 11.09.2024 20:59, Carlos Bilbao wrote: Include a new section in the Index of Further Kernel Documentation with resources to learn Rust. Reference it in the Rust index. Many thanks for creating the patch! Looks nice :) Whats about adding https://google.github.io/comprehensive-rust/ https:/

[PATCH] kernel-docs: Add new section for Rust learning materials

Include a new section in the Index of Further Kernel Documentation with resources to learn Rust. Reference it in the Rust index. Signed-off-by: Carlos Bilbao --- Documentation/process/kernel-docs.rst | 111 +++--- Documentation/rust/index.rst | 3 + 2 files changed

Re: [PATCH 02/12] pci/p2pdma: Don't initialise page refcount to one

On Wed, Sep 11, 2024 at 11:07:51AM +1000, Alistair Popple wrote: > > >> diff --git a/drivers/pci/p2pdma.c b/drivers/pci/p2pdma.c > >> index 4f47a13..210b9f4 100644 > >> --- a/drivers/pci/p2pdma.c > >> +++ b/drivers/pci/p2pdma.c > >> @@ -129,6 +129,12 @@ static int p2pmem_alloc_mmap(struct file *fi

Re: [PATCH 12/12] mm: Remove devmap related functions and page table bits

Hi Alistair, On Tue, 10 Sept 2024 at 12:21, Alistair Popple wrote: > > Now that DAX and all other reference counts to ZONE_DEVICE pages are > managed normally there is no need for the special devmap PTE/PMD/PUD > page table bits. So drop all references to these, freeing up a > software defined pa