On Fri, Sep 21, 2018 at 8:03 AM, Yu-cheng Yu wrote:
> Look in .note.gnu.property of an ELF file and check if Shadow Stack needs
> to be enabled for the task.
Ah, I've been wanting this for other things too (see below).
>
> Signed-off-by: H.J. Lu
> Signed-off-by: Yu-cheng Yu
> ---
> arch/x86/K
On Mon, Oct 15, 2018 at 01:15:56PM -0700, Joel Fernandes wrote:
> On Mon, Oct 15, 2018 at 12:54:26PM -0700, Paul E. McKenney wrote:
> [...]
> > > > In any case, please don't spin for milliseconds with preemption
> > > > disabled.
> > > > The real-time guys are unlikely to be happy with you if you
On Tue 2018-09-25 16:06:56, Jarkko Sakkinen wrote:
> Documentation of the features of the Software Guard eXtensions used
> by the Linux kernel and basic design choices for the core and driver
> and functionality.
>
> Signed-off-by: Jarkko Sakkinen
> --- /dev/null
> +++ b/Documentation/x86/intel_
On Mon, Oct 15, 2018 at 3:11 PM Moritz Fischer
wrote:
>
> On Wed, Sep 26, 2018 at 9:12 AM Alan Tull wrote:
> >
> > Clarify the intention that interfaces and upper layers use
> > regions rather than managers directly.
> >
> > Rearrange API documentation to better group the API functions
> > used t
Hi Greg,
I have two tiny fixes, one for the IDA test-suite and one for the IDR
documentation license.
The following changes since commit f0a7d1883d9f78ae7bf15fc258bf9a2b20f35b76:
afs: Fix clearance of reply (2018-10-15 15:31:47 +0200)
are available in the Git repository at:
git://git.inf
Currently, cpuset.sched.partition returns the values, 0, 1 or -1 on
read. A person who is not familiar with the partition code may not
understand what they mean.
In order to make cpuset.sched.partition more user-friendly, it will
now display the following descriptive text on read:
"normal" - A
A new cpuset.sched.partition boolean flag is added to cpuset v2.
This new flag, if set, indicates that the cgroup is the root of a
new scheduling domain or partition that includes itself and all its
descendants except those that are scheduling domain roots themselves
and their descendants.
With th
In the default hierarchy, a cpuset will use the parent's effective_cpus
if none of the requested CPUs can be granted from the parent. That can
be a problem if a parent is a partition root with children partition
roots. Changes to a parent's effective_cpus list due to changes in a
child partition ro
>From a cpuset point of view, a scheduling partition is a group of
cpusets with their own set of exclusive CPUs that are not shared by
other tasks outside the scheduling partition.
In the legacy hierarchy, scheduling partitions are supported indirectly
via the right use of the load balancing and t
The generate_sched_domains() function is modified to make it work
correctly with the newly introduced subparts_cpus mask for scheduling
domains generation.
Signed-off-by: Waiman Long
---
kernel/cgroup/cpuset.c | 34 +++---
1 file changed, 27 insertions(+), 7 deletions
Because of the fact that setting the "cpuset.sched.partition" in
a direct child of root can remove CPUs from the root's effective CPU
list, it makes sense to know what CPUs are left in the root cgroup for
scheduling purpose. So the "cpuset.cpus.effective" control file is now
exposed in the v2 cgrou
When there is a cpu hotplug event (CPU online or offline), the partitions
may need to be reconfigured and regenerated. So code is added to the
hotplug functions to make them work with new subparts_cpus mask to
compute the right effective_cpus for each of the affected cpusets.
It may also change the
Given the fact that thread mode had been merged into 4.14, it is now
time to enable cpuset to be used in the default hierarchy (cgroup v2)
as it is clearly threaded.
The cpuset controller had experienced feature creep since its
introduction more than a decade ago. Besides the core cpus and mems
co
For debugging purpose, it will be useful to expose the content of the
subparts_cpus as a read-only file to see if the code work correctly.
However, subparts_cpus will not be used at all in most use cases. So
adding a new cpuset file that clutters the cgroup directory may not be
desirable. This is
The previous commit introduces a new subparts_cpus mask into the cpuset
data structure and a new tmpmasks structure. Managing the allocation
and freeing of those cpumasks is becoming more complex.
So a number of helper functions are added to simplify and streamline
the management of those cpumask
The cgroup-v2.rst file is updated to document the purpose of the new
"cpuset.sched.partition" flag and how its usage.
Signed-off-by: Waiman Long
---
Documentation/admin-guide/cgroup-v2.rst | 66 +
1 file changed, 66 insertions(+)
diff --git a/Documentation/admin-guide/cg
v14:
- Fix a bug about cpumask handling in patch 4 by using
CONFIG_CPUMASK_OFFSTACK #ifdef block.
- Add patch 12 to show descriptive name when reading
cpuset.sched.partition (suggested by Tejun).
- Change the function prototype of free_cpumasks() to match that of
alloc_cpumasks() (sugge
Handling error returned by update_parent_subparts_cpumask() in
update_cpumasks_hier() is problematic as the states may become
inconsistent. To avoid that and increase flexibility in handling other
error cases, a new error state (-1) is added to the partition_root_state
flag. This new error state is
On Mon, Oct 15, 2018 at 12:54:26PM -0700, Paul E. McKenney wrote:
[...]
> > > In any case, please don't spin for milliseconds with preemption disabled.
> > > The real-time guys are unlikely to be happy with you if you do this!
> >
> > Well just to clarify, I was just running Oleg's test which did
On Wed, Sep 26, 2018 at 9:12 AM Alan Tull wrote:
>
> Clarify the intention that interfaces and upper layers use
> regions rather than managers directly.
>
> Rearrange API documentation to better group the API functions
> used to create FPGA mgr/bridge/regions and the API used for
> programming FPG
On Wed, Sep 26, 2018 at 9:12 AM Alan Tull wrote:
>
> Add devm_fpga_region_create() which is the
> managed version of fpga_region_create().
>
> Change current region drivers to use
> devm_fpga_region_create().
>
> Signed-off-by: Alan Tull
> Suggested-by: Federico Vaga
Acked-by: Moritz Fischer
>
On Mon, Oct 15, 2018 at 12:39:51PM -0700, Joel Fernandes wrote:
> On Mon, Oct 15, 2018 at 04:21:12AM -0700, Paul E. McKenney wrote:
> > On Mon, Oct 15, 2018 at 09:05:22AM +0300, Nikolay Borisov wrote:
> > > On 15.10.2018 05:47, Joel Fernandes wrote:
> > > > On Sun, Oct 14, 2018 at 07:33:28PM -0700,
On Mon, Oct 15, 2018 at 04:21:12AM -0700, Paul E. McKenney wrote:
> On Mon, Oct 15, 2018 at 09:05:22AM +0300, Nikolay Borisov wrote:
> > On 15.10.2018 05:47, Joel Fernandes wrote:
> > > On Sun, Oct 14, 2018 at 07:33:28PM -0700, Paul E. McKenney wrote:
> > >> On Sun, Oct 14, 2018 at 07:13:49PM -0700
On 10/15/2018 12:41 PM, Waiman Long wrote:
On 10/15/2018 02:31 PM, Tom Hromatka wrote:
On 10/12/2018 11:55 AM, Waiman Long wrote:
Given the fact that thread mode had been merged into 4.14, it is now
time to enable cpuset to be used in the default hierarchy (cgroup v2)
as it is clearly threa
On 10/15/2018 02:35 PM, Tom Hromatka wrote:
>
>
> On 10/12/2018 11:55 AM, Waiman Long wrote:
>> The previous commit introduces a new subparts_cpus mask into the cpuset
>> data structure and a new tmpmasks structure. Managing the allocation
>> and freeing of those cpumasks is becoming more complex.
On 10/15/2018 02:31 PM, Tom Hromatka wrote:
>
>
> On 10/12/2018 11:55 AM, Waiman Long wrote:
>> Given the fact that thread mode had been merged into 4.14, it is now
>> time to enable cpuset to be used in the default hierarchy (cgroup v2)
>> as it is clearly threaded.
>>
>> The cpuset controller had
On 10/12/2018 11:55 AM, Waiman Long wrote:
The previous commit introduces a new subparts_cpus mask into the cpuset
data structure and a new tmpmasks structure. Managing the allocation
and freeing of those cpumasks is becoming more complex.
So a number of helper functions are added to simplif
On 10/12/2018 11:55 AM, Waiman Long wrote:
Given the fact that thread mode had been merged into 4.14, it is now
time to enable cpuset to be used in the default hierarchy (cgroup v2)
as it is clearly threaded.
The cpuset controller had experienced feature creep since its
introduction more than
On Sat, Oct 13, 2018 at 09:47:46PM +, Will Korteland wrote:
> This patch fixes a minor, incorrect piece of grammar in the UIO howto.
>
> Signed-off-by: Will Korteland
> Acked-by: Randy Dunlap
> ---
> This is my first attempt at a kernel patch, so please let me know if
> I've done something s
This commit adds PECI adapter driver implementation for Aspeed
AST24xx/AST25xx SoCs.
Cc: Joel Stanley
Cc: Andrew Jeffery
Cc: Andy Shevchenko
Cc: Greg Kroah-Hartman
Cc: Robin Murphy
Cc: Ryan Chen
Signed-off-by: Jae Hyun Yoo
Reviewed-by: Haiyue Wang
Reviewed-by: James Feist
Reviewed-by: Ver
This commit adds PECI bus/adapter node of AST24xx/AST25xx into
aspeed-g4 and aspeed-g5.
Cc: Rob Herring
Cc: Mark Rutland
Cc: Joel Stanley
Cc: Andrew Jeffery
Cc: Jason M Biils
Cc: Ryan Chen
Signed-off-by: Jae Hyun Yoo
Reviewed-by: Haiyue Wang
Reviewed-by: James Feist
Reviewed-by: Vernon Ma
This commit adds a dt-bindings document of PECI adapter driver for ASPEED
AST24xx/25xx SoCs.
Cc: Mark Rutland
Cc: Joel Stanley
Cc: Andrew Jeffery
Cc: Benjamin Herrenschmidt
Cc: Greg Kroah-Hartman
Cc: Jason M Biils
Cc: Milton Miller II
Cc: Pavel Machek
Cc: Robin Murphy
Cc: Ryan Chen
Signe
This commit adds maintainer information for the PECI subsystem.
Cc: David S. Miller
Cc: Mauro Carvalho Chehab
Cc: Greg Kroah-Hartman
Cc: Andrew Morton
Cc: Linus Walleij
Cc: Randy Dunlap
Cc: Jason M Biils
Signed-off-by: Jae Hyun Yoo
---
MAINTAINERS | 13 +
1 file changed, 13 in
This commit adds hwmon documents for PECI cputemp and dimmtemp drivers.
Cc: Guenter Roeck
Cc: Jean Delvare
Cc: Jonathan Corbet
Cc: Jason M Biils
Cc: Randy Dunlap
Signed-off-by: Jae Hyun Yoo
Reviewed-by: Haiyue Wang
Reviewed-by: James Feist
Reviewed-by: Vernon Mauery
Acked-by: Guenter Roec
This commit adds PECI client MFD driver.
Cc: Lee Jones
Cc: Randy Dunlap
Cc: Rob Herring
Cc: Andrew Jeffery
Cc: James Feist
Cc: Jason M Biils
Cc: Joel Stanley
Cc: Vernon Mauery
Signed-off-by: Jae Hyun Yoo
---
drivers/mfd/Kconfig | 14 ++
drivers/mfd/Makefile
This commit adds a dt-bindings document for PECI client MFD.
Cc: Lee Jones
Cc: Rob Herring
Cc: Mark Rutland
Cc: Andrew Jeffery
Cc: James Feist
Cc: Jason M Biils
Cc: Joel Stanley
Cc: Vernon Mauery
Signed-off-by: Jae Hyun Yoo
Reviewed-by: Rob Herring
---
.../bindings/mfd/intel-peci-client
This commit adds PECI cputemp hwmon driver.
Cc: Guenter Roeck
Cc: Jean Delvare
Cc: Alan Cox
Cc: Andrew Jeffery
Cc: Andy Shevchenko
Cc: Arnd Bergmann
Cc: Jason M Biils
Cc: Joel Stanley
Cc: Miguel Ojeda
Cc: Andrew Lunn
Cc: Stef van Os
Signed-off-by: Jae Hyun Yoo
Reviewed-by: Haiyue Wang
This commit adds PECI dimmtemp hwmon driver.
Cc: Guenter Roeck
Cc: Jean Delvare
Cc: Alan Cox
Cc: Andrew Jeffery
Cc: Andy Shevchenko
Cc: Arnd Bergmann
Cc: Jason M Biils
Cc: Joel Stanley
Cc: Miguel Ojeda
Cc: Andrew Lunn
Cc: Stef van Os
Signed-off-by: Jae Hyun Yoo
Reviewed-by: Haiyue Wang
This commit adds driver implementation for PECI bus core into linux
driver framework.
Cc: Greg Kroah-Hartman
Cc: Philippe Ombredanne
Cc: Gavin Schenk
Cc: Vinod Koul
Cc: Thomas Gleixner
Cc: Sagar Dharia
Cc: David Kershner
Cc: Johan Hovold
Cc: Uwe Kleine-Konig
Cc: Viresh Kumar
Cc: Randy Du
Introduction of the Platform Environment Control Interface (PECI) bus
device driver. PECI is a one-wire bus interface that provides a
communication channel from Intel processors and chipset components to
external monitoring or control devices. PECI is designed to support the
following sideband func
This commit updates ioctl-number.txt to reflect ioctl numbers used
by the PECI subsystem.
Cc: Jonathan Corbet
Cc: Greg Kroah-Hartman
Cc: Kishon Vijay Abraham I
Cc: Lorenzo Pieralisi
Cc: Gustavo Pimentel
Cc: Darrick J. Wong
Cc: Tomohiro Kusumi
Cc: Eric Sandeen
Cc: Frederic Barrat
Cc: Bryan
This commit adds a document of generic PECI bus, adapter and client
driver.
Cc: Rob Herring
Cc: Mark Rutland
Cc: Andrew Jeffery
Cc: Joel Stanley
Signed-off-by: Jae Hyun Yoo
Reviewed-by: Haiyue Wang
Reviewed-by: James Feist
Reviewed-by: Vernon Mauery
Reviewed-by: Rob Herring
---
.../devic
Hi Alan,
On Mon, Oct 15, 2018 at 7:55 AM Alan Tull wrote:
>
> On Wed, Sep 26, 2018 at 11:12 AM Alan Tull wrote:
>
> Any other comments on this patchset?
Looks good to me, Sorry for the delay
Acked-by: Moritz Fischer
Cheers,
Moritz
The Continuous Performance Control Package can have guaranteed performance
field. Add support to read guaranteed performance.
Signed-off-by: Srinivas Pandruvada
---
drivers/acpi/cppc_acpi.c | 8 ++--
include/acpi/cppc_acpi.h | 1 +
2 files changed, 7 insertions(+), 2 deletions(-)
diff --git
This series presents base frequency to cpufreq sysfs when intel_pstate
is in use in HWP mode.
Changes:
v4:
- Documentation update only as suggested by Rafael
v3:
- Update documentation
v2
- Removed guaranteed attribute addition to acpi_cppc sysfs
- Using the cppc_acpi interface to get base freque
Present base_frequency to user space via cpufreq sysfs when HWP is in
use.
This HWP base frequency is read from HWP Capabilities MSR, if platform
doesn't have ACPI _CPC object. On most of the HWP platforms the _CPC
object will point to the HWP Capabilities MSR using address space id as
"Functional
Updated documentation to explain base_frequency attribute.
Suggested-by: Rafael J. Wysocki
Signed-off-by: Srinivas Pandruvada
---
Documentation/admin-guide/pm/intel_pstate.rst | 7 +++
1 file changed, 7 insertions(+)
diff --git a/Documentation/admin-guide/pm/intel_pstate.rst
b/Documentati
On 10/15/2018 12:35 PM, Tejun Heo wrote:
> Hello, Waiman.
>
> This looks great to me. I have only one small nit in terms of
> interface. Currently, cpuset.partition file uses -1, 0, 1; however,
> given that this is consistent with how cgroup.type behaves (something
> can be set but may be invalid
On Thu, Oct 11, 2018 at 08:14:58AM -0700, Yu-cheng Yu wrote:
> Control Flow Enforcement (CET) MSRs are XSAVES system/supervisor
> states. To support CET, we introduce XSAVES system states first.
>
> XSAVES is a "supervisor" instruction and, comparing to XSAVE, saves
> additional "supervisor" stat
Hello, Waiman.
This looks great to me. I have only one small nit in terms of
interface. Currently, cpuset.partition file uses -1, 0, 1; however,
given that this is consistent with how cgroup.type behaves (something
can be set but may be invalid), I wonder whether using a similar
syntax would be
On 10/15/18 1:10 AM, Will Korteland wrote:
> This patch fixes a minor, incorrect piece of grammar in the UIO howto.
>
> Signed-off-by: Will Korteland
Looks good to me. Thanks.
Acked-by: Randy Dunlap
> ---
> This is my first attempt at a kernel patch, so please let me know if
> I've done som
On Mon, 2018-10-15 at 10:53 +0200, Rafael J. Wysocki wrote:
> On Fri, Oct 12, 2018 at 6:44 PM Srinivas Pandruvada
> wrote:
> >
> > Updated documentation to explain base_frequency attribute.
> >
> > Signed-off-by: Srinivas Pandruvada <
> > srinivas.pandruv...@linux.intel.com>
> > ---
> > Documen
On Wed, Sep 26, 2018 at 11:12 AM Alan Tull wrote:
Any other comments on this patchset?
Alan
>
> Add devm_fpga_mgr_create() which is the managed
> version of fpga_mgr_create().
>
> Change current FPGA manager drivers to use
> devm_fpga_mgr_create()
>
> Signed-off-by: Alan Tull
> Suggested-by: F
On Mon, 15 Oct 2018 02:55:49 -0700
Christoph Hellwig wrote:
> > OK, I've had a long conversation with the LF lawyer, and she said clearly
> > that we really should not be introducing CC-SA material into the kernel
> > source tree. It's a pain; I really do like CC-SA better for
> > documentation,
On 15/10/18 13:00, han...@marvell.com wrote:
From: Hanna Hawa
Add specific compatible string for Marvell usage due errata of
accessing 64bit registers of ARM SMMU, in AP806.
AP806 SOC use the generic ARM-MMU500, and there's no specific
implementation of Marvell, this compatible is used for err
Hi Hanna,
On 15/10/18 13:00, han...@marvell.com wrote:
From: Hanna Hawa
Due to erratum #582743, the Marvell Armada-AP806 can't access 64bit
to ARM SMMUv2 registers.
This patch split the writeq/readq to two accesses of writel/readl.
Note that separate writes/reads to 2 is not problem regards t
From: Hanna Hawa
Add specific compatible string for Marvell usage due errata of
accessing 64bit registers of ARM SMMU, in AP806.
AP806 SOC use the generic ARM-MMU500, and there's no specific
implementation of Marvell, this compatible is used for errata only.
Signed-off-by: Hanna Hawa
---
Docu
From: Hanna Hawa
Due to erratum #582743, the Marvell Armada-AP806 can't access 64bit
to ARM SMMUv2 registers.
This patch split the writeq/readq to two accesses of writel/readl.
Note that separate writes/reads to 2 is not problem regards to atomicity,
because the driver use the readq/writeq while
From: Hanna Hawa
This series add support for IOMMU for AP806, including workaround
for accessing ARM SMMU 64bit registers.
AP-806 can't access SMMU registers with 64bit width, this patches split
the readq/writeq for 32bit access, due to erratanum #582743.
Hanna Hawa (4):
iommu/arm-smmu: introd
From: Hanna Hawa
This patch introduce the smmu_writeq_relaxed/smmu_readq_relaxed
helpers, as preparation to add specific Marvell work-around for
accessing 64bit width registers of ARM SMMU.
Signed-off-by: Hanna Hawa
---
drivers/iommu/arm-smmu.c | 36 +++-
1 file
From: Hanna Hawa
Add SMMU node for Marvell Armada-AP806 SOC.
Signed-off-by: Hanna Hawa
---
arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 17 +
1 file changed, 17 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
b/arch/arm64/boot/dts/marvell/armada-ap
On Mon, Oct 15, 2018 at 09:05:22AM +0300, Nikolay Borisov wrote:
> On 15.10.2018 05:47, Joel Fernandes wrote:
> > On Sun, Oct 14, 2018 at 07:33:28PM -0700, Paul E. McKenney wrote:
> >> On Sun, Oct 14, 2018 at 07:13:49PM -0700, Joel Fernandes wrote:
> >>> On Sun, Oct 14, 2018 at 07:08:27PM -0700, Jo
On Thu, Oct 11, 2018 at 11:27:35AM -0600, Jonathan Corbet wrote:
> On Sat, 6 Oct 2018 10:51:54 +1000
> Dave Chinner wrote:
>
> > Can you let us know whether the CC-by-SA 4.0 license is acceptible
> > or not? That's really the only thing that we need clarified at this
> > point - if it's OK I'll t
On Fri, Oct 12, 2018 at 6:44 PM Srinivas Pandruvada
wrote:
>
> Updated documentation to explain base_frequency attribute.
>
> Signed-off-by: Srinivas Pandruvada
> ---
> Documentation/admin-guide/pm/intel_pstate.rst | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/Documentation/admin-
This patch fixes a minor, incorrect piece of grammar in the UIO howto.
Signed-off-by: Will Korteland
---
This is my first attempt at a kernel patch, so please let me know if
I've done something silly. I sent a copy of this a few days ago, but
I can't find it on the public archives - apologies i
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