On Wed, Oct 10, 2018 at 04:36:56PM +0100, Catalin Marinas wrote:
> On Wed, Oct 10, 2018 at 04:10:21PM +0200, Eugene Syromiatnikov wrote:
> > I have some questions regarding AArch64 ILP32 implementation for which I
> > failed to find an answer myself:
> > * How ptrace() tracer is supposed to distin
On Wed, Oct 10, 2018 at 03:39:07PM +0100, Szabolcs Nagy wrote:
> On 10/10/18 15:10, Eugene Syromiatnikov wrote:
> > * What's the reasoning behind capping syscall arguments to 32 bit? x32
> >and MIPS N32 do not have such a restriction (and do not need special
> >wrappers for syscalls that p
On Thu, 2018-10-11 at 13:55 -0700, Andy Lutomirski wrote:
> On Thu, Oct 11, 2018 at 1:39 PM Jann Horn wrote:
> >
> > On Thu, Oct 11, 2018 at 5:20 PM Yu-cheng Yu wrote:
> > > Create a guard area between VMAs to detect memory corruption.
> >
> > [...]
> > > +config VM_AREA_GUARD
> > > + boo
On Friday, October 12, 2018 3:19 AM, John Johansen
wrote:
> It isn't perfect but it manages consistency across distros as best as
> can be achieved atm.
Yeah, this is why I'm okay with the current series: it provides as
consistent a view as possible, but leaves room for future improvements
(like
On 10/12/2018 04:31 AM, Jordan Glover wrote:
> Sent with ProtonMail Secure Email.
>
> ‐‐‐ Original Message ‐‐‐
> On Friday, October 12, 2018 3:19 AM, John Johansen
> wrote:
>>
>> It isn't perfect but it manages consistency across distros as best as
>> can be achieved atm.
>>
>> Its just
On 10/12/2018 04:31 AM, Jordan Glover wrote:
> ‐‐‐ Original Message ‐‐‐
> On Friday, October 12, 2018 2:26 AM, John Johansen
> wrote:
>
>> On 10/11/2018 04:53 PM, Jordan Glover wrote:
>>
>>> ‐‐‐ Original Message ‐‐‐
>>> On Friday, October 12, 2018 1:09 AM, Kees Cook keesc...@chro
In the default hierarchy, a cpuset will use the parent's effective_cpus
if none of the requested CPUs can be granted from the parent. That can
be a problem if a parent is a partition root with children partition
roots. Changes to a parent's effective_cpus list due to changes in a
child partition ro
The previous commit introduces a new subparts_cpus mask into the cpuset
data structure and a new tmpmasks structure. Managing the allocation
and freeing of those cpumasks is becoming more complex.
So a number of helper functions are added to simplify and streamline
the management of those cpumask
v13:
- A major rewrite of the partition code so that there will be no
auto-turning off anymore. Instead, the partition root can enter into
an error state that can be restored back to a partition root later on.
- Patches 1 and 9 are the same as previous version, the rests are
either new o
The generate_sched_domains() function is modified to make it work
correctly with the newly introduced subparts_cpus mask for scheduling
domains generation.
Signed-off-by: Waiman Long
---
kernel/cgroup/cpuset.c | 34 +++---
1 file changed, 27 insertions(+), 7 deletions
>From a cpuset point of view, a scheduling partition is a group of
cpusets with their own set of exclusive CPUs that are not shared by
other tasks outside the scheduling partition.
In the legacy hierarchy, scheduling partitions are supported indirectly
via the right use of the load balancing and t
Given the fact that thread mode had been merged into 4.14, it is now
time to enable cpuset to be used in the default hierarchy (cgroup v2)
as it is clearly threaded.
The cpuset controller had experienced feature creep since its
introduction more than a decade ago. Besides the core cpus and mems
co
When there is a cpu hotplug event (CPU online or offline), the partitions
may need to be reconfigured and regenerated. So code is added to the
hotplug functions to make them work with new subparts_cpus mask to
compute the right effective_cpus for each of the affected cpusets.
It may also change the
The cgroup-v2.rst file is updated to document the purpose of the new
"cpuset.sched.partition" flag and how its usage.
Signed-off-by: Waiman Long
---
Documentation/admin-guide/cgroup-v2.rst | 66 +
1 file changed, 66 insertions(+)
diff --git a/Documentation/admin-
Because of the fact that setting the "cpuset.sched.partition" in
a direct child of root can remove CPUs from the root's effective CPU
list, it makes sense to know what CPUs are left in the root cgroup for
scheduling purpose. So the "cpuset.cpus.effective" control file is now
exposed in the v2 cgrou
For debugging purpose, it will be useful to expose the content of the
subparts_cpus as a read-only file to see if the code work correctly.
However, subparts_cpus will not be used at all in most use cases. So
adding a new cpuset file that clutters the cgroup directory may not be
desirable. This is
A new cpuset.sched.partition boolean flag is added to cpuset v2.
This new flag, if set, indicates that the cgroup is the root of a
new scheduling domain or partition that includes itself and all its
descendants except those that are scheduling domain roots themselves
and their descendants.
With th
Handling error returned by update_parent_subparts_cpumask() in
update_cpumasks_hier() is problematic as the states may become
inconsistent. To avoid that and increase flexibility in handling other
error cases, a new error state (-1) is added to the partition_root_state
flag. This new error state is
On 2018-10-12 11:30 a.m., Jonathan Corbet wrote:
> On Wed, 10 Oct 2018 20:33:08 +0800
> Wesley Sheng wrote:
>
>> The ntb_hw_switchtec driver has requirements on kernel configuration
>> so we add these notes to the documentation and also clean up a few
>> other sentences in the documentation.
On Mon, 8 Oct 2018 13:08:48 +0200
Geert Uytterhoeven wrote:
> When converting from text to rst, the kobjects section and its sole
> subsection about device tree nodes were coalesced into a single section,
> yielding an inconsistent result.
>
> Remove all references to kobjects, as
> 1. Device
On Mon, 8 Oct 2018 14:15:15 +0100
Andrew Murray wrote:
> The existing wording implies that the use of spin_unlock whilst irqs are
> disabled might trigger a reschedule. However the preemptible() test in
> preempt_schedule will prevent a reschedule if irqs are disabled.
>
> Lets improve the clar
On Tue, 9 Oct 2018 11:31:31 +0300
Nikolay Borisov wrote:
> Commit ef548c551e72 ("dm flakey: introduce "error_writes" feature")
> added the ability to dm flakey to error out writes in contrast to
> silently dropping it with 'drop_writes'. Unfortunately this feature
> is not currently documented a
On Wed, 10 Oct 2018 20:33:08 +0800
Wesley Sheng wrote:
> The ntb_hw_switchtec driver has requirements on kernel configuration
> so we add these notes to the documentation and also clean up a few
> other sentences in the documentation.
>
> Signed-off-by: Wesley Yung
> Signed-off-by: Kelvin Cao
On Wed, 10 Oct 2018 22:56:32 +0800
John Garry wrote:
> This patch fixes a couple of punctuation nits which can make the document
> more correct and readable.
>
> Also missing "()" are added to some function references for consistency.
>
> Signed-off-by: John Garry
Applied, thanks.
I agree wi
On Thu, 11 Oct 2018 07:58:15 +0300
Mike Rapoport wrote:
> As discussed at [1], the latest updates to memory hotplug documentation are
> causing a conflict between docs and mmotm trees.
> These patches resolve the conflict.
>
> [1] https://lkml.org/lkml/2018/10/8/227
>
> David Hildenbrand (1):
>
Updated documentation to explain base_frequency attribute.
Signed-off-by: Srinivas Pandruvada
---
Documentation/admin-guide/pm/intel_pstate.rst | 4
1 file changed, 4 insertions(+)
diff --git a/Documentation/admin-guide/pm/intel_pstate.rst
b/Documentation/admin-guide/pm/intel_pstate.rst
i
Present base_frequency to user space via cpufreq sysfs when HWP is in
use.
This HWP base frequency is read from HWP Capabilities MSR, if platform
doesn't have ACPI _CPC object. On most of the HWP platforms the _CPC
object will point to the HWP Capabilities MSR using address space id as
"Functional
The Continuous Performance Control Package can have guaranteed performance
field. Add support to read guaranteed performance.
Signed-off-by: Srinivas Pandruvada
---
drivers/acpi/cppc_acpi.c | 8 ++--
include/acpi/cppc_acpi.h | 1 +
2 files changed, 7 insertions(+), 2 deletions(-)
diff --git
This series presents base frequency to cpufreq sysfs when intel_pstate
is in use in HWP mode.
Changes:
v3:
- Update documentation
v2
- Removed guaranteed attribute addition to acpi_cppc sysfs
- Using the cppc_acpi interface to get base frequency and present
Srinivas Pandruvada (3):
ACPI / CPPC:
On Thu, Oct 11, 2018 at 10:39:24PM +0200, Jann Horn wrote:
> Sorry to bring this up so late, but Daniel Micay pointed out to me
> that, given that VMA guards will raise the number of VMAs by
> inhibiting vma_merge(), people are more likely to run into
> /proc/sys/vm/max_map_count (which limits the
On 12.10.2018 15:15, Thierry Reding wrote:
> On Tue, Aug 28, 2018 at 04:01:25PM +0300, Claudiu Beznea wrote:
>> Add documentation for PWM push-pull mode.
>>
>> Signed-off-by: Claudiu Beznea
>> Reviewed-by: Rob Herring
>> ---
>> Documentation/devicetree/bindings/pwm/pwm.txt | 2 ++
>> Documen
On Sat, Sep 01, 2018 at 08:06:16PM +0800, kbuild test robot wrote:
> Hi Eddie,
>
> I love your patch! Yet something to improve:
>
> [auto build test ERROR on hwmon/hwmon-next]
> [also build test ERROR on v4.19-rc1 next-20180831]
> [if your patch is applied to the wrong git tree, please drop us a
On Wed, Sep 12, 2018 at 09:56:33AM +0200, Benjamin Herrenschmidt wrote:
> On Mon, 2018-09-10 at 13:16 -0500, Rob Herring wrote:
> > On Thu, Aug 30, 2018 at 04:32:32PM -0500, Eddie James wrote:
> > > Document the bindings for the FSI-attached POWER9 On-Chip Controller.
> > >
> > > Signed-off-by: Ed
On Tue, Aug 28, 2018 at 04:01:25PM +0300, Claudiu Beznea wrote:
> Add documentation for PWM push-pull mode.
>
> Signed-off-by: Claudiu Beznea
> Reviewed-by: Rob Herring
> ---
> Documentation/devicetree/bindings/pwm/pwm.txt | 2 ++
> Documentation/pwm.txt | 16 ++
Hello my dear.
Did you receive my email message to you? Please, get back to me ASAP as the
matter is becoming late. Expecting your urgent response.
Sean.
Sent with ProtonMail Secure Email.
‐‐‐ Original Message ‐‐‐
On Friday, October 12, 2018 3:19 AM, John Johansen
wrote:
>
> It isn't perfect but it manages consistency across distros as best as
> can be achieved atm.
>
> Its just a fact that some LSMs are not going to be built into some
>
‐‐‐ Original Message ‐‐‐
On Friday, October 12, 2018 2:26 AM, John Johansen
wrote:
> On 10/11/2018 04:53 PM, Jordan Glover wrote:
>
> > ‐‐‐ Original Message ‐‐‐
> > On Friday, October 12, 2018 1:09 AM, Kees Cook keesc...@chromium.org wrote:
> >
> > > We've had things sort of like
Hi Petr,
On Fri, Oct 12, 2018 at 12:39 PM Petr Mladek wrote:
> On Thu 2018-10-11 10:42:47, Geert Uytterhoeven wrote:
> > - Make the ptr argument const, to avoid adding casts in future
> > callers,
> > - Move the function and its dependencies up, so it can be called from
> > special po
On Fri, Oct 12, 2018 at 12:40:53PM +0200, Thierry Reding wrote:
> On Tue, Aug 21, 2018 at 07:16:24PM +0200, Paul Cercueil wrote:
> > The TCU channels 0 and 1 were previously reserved for system tasks, and
> > thus unavailable for PWM.
> >
> > This commit uses the newly introduced API functions of
On Fri, Oct 12, 2018 at 12:41:50PM +0200, Thierry Reding wrote:
> On Tue, Aug 21, 2018 at 07:16:25PM +0200, Paul Cercueil wrote:
> > Depending on MACH_INGENIC prevent us from creating a generic kernel that
> > works on more than one MIPS board. Instead, we just depend on MIPS being
> > set.
> >
>
On Tue, Aug 21, 2018 at 07:16:27PM +0200, Paul Cercueil wrote:
> The PWM in the JZ4725B works the same as in the JZ4740, except that it
> only has 6 channels available instead of 8.
>
> Signed-off-by: Paul Cercueil
> ---
>
> Notes:
> v5: New patch
>
> v6: - Move of_device_id struc
On Tue, Aug 21, 2018 at 07:16:26PM +0200, Paul Cercueil wrote:
> Right now none of the Ingenic-based boards probe this driver from
> devicetree. This driver defined three compatible strings for the exact
> same behaviour. Before these strings are used, we can remove two of
> them.
>
> Signed-off-b
On Tue, Aug 21, 2018 at 07:16:25PM +0200, Paul Cercueil wrote:
> Depending on MACH_INGENIC prevent us from creating a generic kernel that
> works on more than one MIPS board. Instead, we just depend on MIPS being
> set.
>
> On other architectures, this driver can still be built, thanks to
> COMPIL
On Tue, Aug 21, 2018 at 07:16:24PM +0200, Paul Cercueil wrote:
> The TCU channels 0 and 1 were previously reserved for system tasks, and
> thus unavailable for PWM.
>
> This commit uses the newly introduced API functions of the ingenic-timer
> driver to request/release the TCU channels that should
On Thu 2018-10-11 10:42:48, Geert Uytterhoeven wrote:
> On platforms using the Common Clock Framework, "%pC" prints the clock's
> name. On legacy platforms, it prints the unhashed clock's address,
> potentially leaking sensitive information regarding the kernel layout in
> memory.
>
> Avoid this l
On Thu 2018-10-11 10:42:49, Geert Uytterhoeven wrote:
> The handler for "%pN" falls back to printing the raw pointer value when
> using a different format than the (sole supported) special format
> "%pNF", potentially leaking sensitive information regarding the kernel
> layout in memory.
>
> Avoid
On Tue, Aug 21, 2018 at 07:16:23PM +0200, Paul Cercueil wrote:
> The ingenic-timer "TCU" driver provides us with a regmap, that we can
> use to safely access the TCU registers.
>
> It also provides us with clocks, that can be (un)gated, reparented or
> reclocked from devicetree, instead of having
On Thu 2018-10-11 10:42:47, Geert Uytterhoeven wrote:
> - Make the ptr argument const, to avoid adding casts in future
> callers,
> - Move the function and its dependencies up, so it can be called from
> special pointer type formatting routines.
>
> Signed-off-by: Geert Uytterhoeven
* Dave Hansen:
> On 10/11/2018 08:15 AM, Yu-cheng Yu wrote:
>> Create a guard area between VMAs to detect memory corruption.
>
> This is a pretty major change that has a bunch of end-user implications.
> It's not dependent on any debugging options and can't be turned on/off
> by individual apps,
On Thu, Oct 11, 2018 at 09:46:56PM +0300, Jani Nikula wrote:
> On Thu, 11 Oct 2018, Peter Zijlstra wrote:
> > On Thu, Oct 11, 2018 at 08:29:10AM -0700, Matthew Wilcox wrote:
> >> On Wed, Oct 10, 2018 at 10:56:32PM +0800, John Garry wrote:
> >> > This patch fixes a couple of punctuation nits which
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