On 17/04/18 12:09, Alastair D'Silva wrote:
From: Alastair D'Silva
The function removes the process element from NPU cache.
Signed-off-by: Alastair D'Silva
Hmm, personally I'd suggest pnv_ocxl_spa_clear_cache() because it's just
a wrapper around the OPAL call of a similar name.
But I don
On Tue, 2018-04-17 at 14:21 +1000, Andrew Donnellan wrote:
> On 17/04/18 12:09, Alastair D'Silva wrote:
> > From: Alastair D'Silva
> >
> > Switch the use of TIDR on it's CPU feature, rather than assuming it
> > is available based on architecture.
> >
> > Signed-off-by: Alastair D'Silva
>
> The
From: Ravi Bangoria
Make function names more meaningful by adding vma_ prefix
to them.
Signed-off-by: Ravi Bangoria
Reviewed-by: Jérôme Glisse
---
include/linux/mm.h | 4 ++--
kernel/events/uprobes.c | 14 +++---
2 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/inc
From: Ravi Bangoria
When virtual memory map for binary/library is being prepared, there is
no direct one to one mapping between mmap() and virtual memory area. Ex,
when loader loads the library, it first calls mmap(size = total_size),
where total_size is addition of size of all elf sections that
From: Ravi Bangoria
Userspace Statically Defined Tracepoints[1] are dtrace style markers
inside userspace applications. Applications like PostgreSQL, MySQL,
Pthread, Perl, Python, Java, Ruby, Node.js, libvirt, QEMU, glib etc
have these markers embedded in them. These markers are added by develope
From: Ravi Bangoria
Reference counter gate the invocation of probe. If present,
by default reference count is 0. Kernel needs to increment
it before tracing the probe and decrement it when done. This
is identical to semaphore in Userspace Statically Defined
Tracepoints (USDT).
Document usage of
From: Oleg Nesterov
build_map_info() has a side effect like one need to perform
mmput() when done with the mm. Add mmput() in free_map_info()
so that user does not have to call it explicitly.
Signed-off-by: Oleg Nesterov
Signed-off-by: Ravi Bangoria
---
kernel/events/uprobes.c | 9 ++---
From: Ravi Bangoria
With this, perf buildid-cache will save SDT markers with reference
counter in probe cache. Perf probe will be able to probe markers
having reference counter. Ex,
# readelf -n /tmp/tick | grep -A1 loop2
Name: loop2
... Semaphore: 0x10020036
# ./perf buildi
From: Ravi Bangoria
Given the file(inode) and offset, build_map_info() finds all
existing mm that map the portion of file containing offset.
Exporting these functions and data structure will help to use
them in other set of files.
Signed-off-by: Ravi Bangoria
Reviewed-by: Jérôme Glisse
---
i
From: Ravi Bangoria
map_info is very generic name, rename it to uprobe_map_info.
Renaming will help to export this structure outside of the
file.
Also rename free_map_info() to uprobe_free_map_info() and
build_map_info() to uprobe_build_map_info().
Signed-off-by: Ravi Bangoria
Reviewed-by: Jér
From: Ravi Bangoria
These are generic functions which operates on file offset
and virtual address. Make these functions available outside
of uprobe code so that other can use it as well.
Signed-off-by: Ravi Bangoria
Reviewed-by: Jérôme Glisse
---
include/linux/mm.h | 12
ker
Userspace Statically Defined Tracepoints[1] are dtrace style markers
inside userspace applications. Applications like PostgreSQL, MySQL,
Pthread, Perl, Python, Java, Ruby, Node.js, libvirt, QEMU, glib etc
have these markers embedded in them. These markers are added by developer
at important places
On 17/04/18 12:09, Alastair D'Silva wrote:
From: Alastair D'Silva
Switch the use of TIDR on it's CPU feature, rather than assuming it
is available based on architecture.
Signed-off-by: Alastair D'Silva
There's a use of TIDR in restore_sprs() that's behind the ARCH_300 flag
as well, ideally
On 17/04/18 12:09, Alastair D'Silva wrote:
diff --git a/arch/powerpc/include/asm/switch_to.h
b/arch/powerpc/include/asm/switch_to.h
index be8c9fa23983..5b03d8a82409 100644
--- a/arch/powerpc/include/asm/switch_to.h
+++ b/arch/powerpc/include/asm/switch_to.h
@@ -94,6 +94,5 @@ static inline void c
On 17/04/18 12:09, Alastair D'Silva wrote:
From: Alastair D'Silva
Signed-off-by: Alastair D'Silva
---
Documentation/accelerators/ocxl.rst | 10 ++
1 file changed, 10 insertions(+)
diff --git a/Documentation/accelerators/ocxl.rst
b/Documentation/accelerators/ocxl.rst
index ddcc58d0
From: Alastair D'Silva
The function removes the process element from NPU cache.
Signed-off-by: Alastair D'Silva
---
arch/powerpc/include/asm/pnv-ocxl.h | 2 +-
arch/powerpc/platforms/powernv/ocxl.c | 4 ++--
drivers/misc/ocxl/link.c | 2 +-
3 files changed, 4 insertions(+), 4 de
From: Alastair D'Silva
In order to successfully issue as_notify, an AFU needs to know the TID
to notify, which in turn means that this information should be
available in userspace so it can be communicated to the AFU.
Signed-off-by: Alastair D'Silva
---
drivers/misc/ocxl/context.c | 5 +
From: Alastair D'Silva
In order for a userspace AFU driver to call the Power9 specific
OCXL_IOCTL_ENABLE_P9_WAIT, it needs to verify that it can actually
make that call.
Signed-off-by: Alastair D'Silva
---
drivers/misc/ocxl/file.c | 25 +
include/uapi/misc/ocxl.h | 4 +
From: Alastair D'Silva
Signed-off-by: Alastair D'Silva
---
Documentation/accelerators/ocxl.rst | 10 ++
1 file changed, 10 insertions(+)
diff --git a/Documentation/accelerators/ocxl.rst
b/Documentation/accelerators/ocxl.rst
index ddcc58d01cfb..144595a80a1c 100644
--- a/Documentation/a
From: Alastair D'Silva
Switch the use of TIDR on it's CPU feature, rather than assuming it
is available based on architecture.
Signed-off-by: Alastair D'Silva
---
arch/powerpc/kernel/process.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/kernel/process.c
From: Alastair D'Silva
The current implementation of TID allocation, using a global IDR, may
result in an errant process starving the system of available TIDs.
Instead, use task_pid_nr(), as mentioned by the original author. The
scenario described which prevented it's use is not applicable, as
se
From: Alastair D'Silva
This patch adds a CPU feature bit to show whether the CPU has
the TIDR register available, enabling as_notify/wait in userspace.
Signed-off-by: Alastair D'Silva
---
arch/powerpc/include/asm/cputable.h | 3 ++-
arch/powerpc/include/asm/switch_to.h | 1 -
arch/powerpc/ker
From: Alastair D'Silva
The Power 9 as_notify/wait feature provides a lower latency way to
signal a thread that work is complete. This series enables the use of
this feature from OpenCAPI adapters, as well as addressing a potential
starvation issue when allocating thread IDs.
Alastair D'Silva (7)
On 4/16/2018 4:22 PM, Jae Hyun Yoo wrote:
On 4/16/2018 11:14 AM, Rob Herring wrote:
On Tue, Apr 10, 2018 at 11:32:09AM -0700, Jae Hyun Yoo wrote:
This commit adds dt-bindings documents for PECI cputemp and dimmtemp
client
drivers.
"dt-bindings: hwmon: ..." for the subject.
I'll change the
On 4/16/2018 11:14 AM, Rob Herring wrote:
On Tue, Apr 10, 2018 at 11:32:09AM -0700, Jae Hyun Yoo wrote:
This commit adds dt-bindings documents for PECI cputemp and dimmtemp client
drivers.
"dt-bindings: hwmon: ..." for the subject.
I'll change the subject.
Signed-off-by: Jae Hyun Yoo
Re
On 4/16/2018 11:10 AM, Rob Herring wrote:
On Tue, Apr 10, 2018 at 11:32:06AM -0700, Jae Hyun Yoo wrote:
This commit adds a dt-bindings document of PECI adapter driver for Aspeed
AST24xx/25xx SoCs.
Signed-off-by: Jae Hyun Yoo
Reviewed-by: Haiyue Wang
Reviewed-by: James Feist
Reviewed-by: Vern
Hi Rob,
Thanks for sharing your time. Please see my answers inline.
On 4/16/2018 10:59 AM, Rob Herring wrote:
On Tue, Apr 10, 2018 at 11:32:03AM -0700, Jae Hyun Yoo wrote:
This commit adds documents of generic PECI bus, adapter and client drivers.
"dt-bindings: ..." for the subject prefix pl
On 04/16/18 14:49, Thymo van Beers wrote:
> Some lines used spaces instead of tabs at line start.
> This can cause mangled lines in editors due to inconsistency.
>
> Replace spaces for tabs where appropriate.
>
> Signed-off-by: Thymo van Beers
> ---
> Changes in v2:
> - Rebase against docs-nex
Some lines used spaces instead of tabs at line start.
This can cause mangled lines in editors due to inconsistency.
Replace spaces for tabs where appropriate.
Signed-off-by: Thymo van Beers
---
Changes in v2:
- Rebase against docs-next
- Fix indentation modifications
Documentation/admin-gu
On Mon, Apr 16, 2018 at 02:08:46PM -0600, Jonathan Corbet wrote:
> On Mon, 16 Apr 2018 17:45:01 +0200
> Thymo van Beers wrote:
>
> > Some lines used spaces instead of tabs at line start.
> > This can cause mangled lines in editors due to inconsistency.
> >
> > Replace spaces for tabs where appro
Hello
Greeetings to you please did you get my previous email regarding my
investment proposal last week friday ?
MS.Zeliha ömer faruk
zeliha.omer.fa...@gmail.com
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More
On Sun, 15 Apr 2018 20:36:56 +0300
Mike Rapoport wrote:
> I didn't mean we should keep it as unorganized jumble of stuff and I agree
> that splitting the documentation by audience is better because developers
> are already know how to find it :)
>
> I just thought that putting the doc into the p
On Mon, 16 Apr 2018 17:45:01 +0200
Thymo van Beers wrote:
> Some lines used spaces instead of tabs at line start.
> This can cause mangled lines in editors due to inconsistency.
>
> Replace spaces for tabs where appropriate.
Seems like a fine idea. The patch doesn't apply, though; can you plea
On Wed, 11 Apr 2018 18:33:26 +0200
Christina Quast wrote:
> Here is a small fixup for the documentation. Unless it's too trivial to
> change it.
Applied, thanks.
In the future, though, please send patches inline rather than as
attachments; that way I don't have to clean things up to apply them.
On 04/16/2018 12:35 PM, Mathieu Poirier wrote:
> Adding a section that document how to use the Coresight framework and
> drivers from the perf tools.
>
> Signed-off-by: Mathieu Poirier
> ---
> Documentation/trace/coresight.txt | 50
> +++
> 1 file changed, 50
Field "owner" of struct coresight_desc has been removed a while back but
the documentation was not updated to reflect the changes.
Signed-off-by: Mathieu Poirier
---
Documentation/trace/coresight.txt | 3 ---
1 file changed, 3 deletions(-)
diff --git a/Documentation/trace/coresight.txt
b/Docum
Adding a section that document how to use the Coresight framework and
drivers from the perf tools.
Signed-off-by: Mathieu Poirier
---
Documentation/trace/coresight.txt | 50 +++
1 file changed, 50 insertions(+)
diff --git a/Documentation/trace/coresight.txt
Now that the perf tools CoreSight support is upstream this set adds
documentation to go with it and move things around so that topics
are located together.
Mathieu Poirier (3):
coresight: Remove obsolete reference to "owner" in CoreSight
descriptor
coresight: Add section for integration
This patch groups together section pertaining to the perf tools. That way
everything is at the same place rather than spread out.
Signed-off-by: Mathieu Poirier
---
Documentation/trace/coresight.txt | 72 +++
1 file changed, 36 insertions(+), 36 deletions(-)
On Tue, Apr 10, 2018 at 11:32:09AM -0700, Jae Hyun Yoo wrote:
> This commit adds dt-bindings documents for PECI cputemp and dimmtemp client
> drivers.
"dt-bindings: hwmon: ..." for the subject.
>
> Signed-off-by: Jae Hyun Yoo
> Reviewed-by: Haiyue Wang
> Reviewed-by: James Feist
> Reviewed-by
On Tue, Apr 10, 2018 at 11:32:06AM -0700, Jae Hyun Yoo wrote:
> This commit adds a dt-bindings document of PECI adapter driver for Aspeed
> AST24xx/25xx SoCs.
>
> Signed-off-by: Jae Hyun Yoo
> Reviewed-by: Haiyue Wang
> Reviewed-by: James Feist
> Reviewed-by: Vernon Mauery
> Cc: Alan Cox
> Cc
On Tue, Apr 10, 2018 at 11:32:03AM -0700, Jae Hyun Yoo wrote:
> This commit adds documents of generic PECI bus, adapter and client drivers.
"dt-bindings: ..." for the subject prefix please.
>
> Signed-off-by: Jae Hyun Yoo
> Reviewed-by: Haiyue Wang
> Reviewed-by: James Feist
> Reviewed-by: Ve
Some lines used spaces instead of tabs at line start.
This can cause mangled lines in editors due to inconsistency.
Replace spaces for tabs where appropriate.
Signed-off-by: Thymo van Beers
---
Documentation/admin-guide/kernel-parameters.txt | 168
1 file changed, 84 in
Hi Gustavo,
On Tuesday 10 April 2018 10:44 PM, Gustavo Pimentel wrote:
> Changes the pcie_raise_irq function signature, namely the interrupt_num
> variable type from u8 to u16 to accommodate the MSI-X maximum interrupts
> of 2048.
>
> Implements a PCIe config space capability iterator function to
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