The movable_node option is a boot-time switch to make sure the physical
NUMA nodes can be hot-added/removed when ACPI table can't be parsed to
provide the memory hotplug information.
As we all know, there is always one node, called "home node", which
can't be movabled and the kernel image resides
On Mon, 02 Apr 2018 05:31:22 PDT (-0700), alan...@andestech.com wrote:
This implements the baseline PMU for RISC-V platforms.
To ease future PMU portings, a guide is also written, containing
perf concepts, arch porting practices and some hints.
Changes in v2:
- Fix the bug reported by Alex, wh
This works for cycle and instruction counts.
Alex
On Mon, Apr 2, 2018 at 5:31 AM, Alan Kao wrote:
>
> This patch provide a basic PMU, riscv_base_pmu, which supports two
> general hardware event, instructions and cycles. Furthermore, this
> PMU serves as a reference implementation to ease the po
On Fri, Mar 30, 2018 at 11:15:24AM +0800, Leo Yan wrote:
> ETMv4 hardware information and configuration needs to be saved as
> metadata; the metadata format should be compatible with 'perf' tool and
> finally is used by tracing data decoder. ETMv4 works as tracer per CPU,
> we cannot wait for gath
On Fri, Mar 30, 2018 at 11:15:23AM +0800, Leo Yan wrote:
> If Coresight path is enabled for specific CPU, the sink device handler
> need to be set to kdump node; on the other hand we also need to clear
> sink device handler when path is disabled.
>
> This patch sets sink devices handler for kdump
On Fri, Mar 30, 2018 at 11:15:22AM +0800, Leo Yan wrote:
> Since Coresight panic kdump functionality has been ready, this patch is
> to hook panic callback function for ETB/ETF driver. The driver data
> structure has allocated a buffer when the session started, so simply
> save tracing data into t
On Fri, Mar 30, 2018 at 11:15:21AM +0800, Leo Yan wrote:
> After kernel panic happens, Coresight tracing data has much useful info
> which can be used for analysis. For example, the trace info from ETB
> RAM can be used to check the CPU execution flows before the crash. So
> we can save the traci
On Mon, 2 Apr 2018, Russell King - ARM Linux wrote:
> On Mon, Apr 02, 2018 at 02:08:13PM -0400, Nicolas Pitre wrote:
> > On Mon, 2 Apr 2018, Abbott Liu wrote:
> >
> > > index c79b829..20161e2 100644
> > > --- a/arch/arm/kernel/head-common.S
> > > +++ b/arch/arm/kernel/head-common.S
> > > @@ -115,
On Mon, Apr 02, 2018 at 02:08:13PM -0400, Nicolas Pitre wrote:
> On Mon, 2 Apr 2018, Abbott Liu wrote:
>
> > index c79b829..20161e2 100644
> > --- a/arch/arm/kernel/head-common.S
> > +++ b/arch/arm/kernel/head-common.S
> > @@ -115,6 +115,9 @@ __mmap_switched:
> > str r8, [r2]
On Mon, 2 Apr 2018, Abbott Liu wrote:
> index c79b829..20161e2 100644
> --- a/arch/arm/kernel/head-common.S
> +++ b/arch/arm/kernel/head-common.S
> @@ -115,6 +115,9 @@ __mmap_switched:
> str r8, [r2]@ Save atags pointer
> cmp r3, #0
> strne r10,
On Fri, Mar 30, 2018 at 11:15:20AM +0800, Leo Yan wrote:
> Add detailed documentation for Coresight panic kdump, which contains
> the idea for why need Coresight panic kdump and introduce the
> implementation of Coresight panic kdump framework; the last section is
> to explain what's usage.
>
> Cr
Hi Leo,
Please see below (and in upcoming patches) my comments related to your latest
work.
Thanks,
Mathieu
On Fri, Mar 30, 2018 at 11:15:18AM +0800, Leo Yan wrote:
> This patch set is to explore Coresight tracing data for postmortem
> debugging. When kernel panic happens, the Coresight panic k
The following changes since commit
7928b2cbe55b2a410a0f5c1f154610059c57b1b2:
Linux 4.16-rc1 (2018-02-11 15:04:29 -0800)
are available in the Git repository at:
git://git.lwn.net/linux.git tags/docs-4.17
for you to fetch changes up to 86afad7d87f535ebb1a0e978bc32a8c58ac99268:
Documentatio
At the mentioned address there's nothing found. By searching information
on the controller chip still can be found, so update the link to the
resulting page.
Signed-off-by: Martin Kepplinger
---
drivers/input/touchscreen/mk712.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a
The input/touchscreen/mk712.c driver has been rewritten for the common
input event system. in 2005. There shouldn't a special device node be
created anymore.
Signed-off-by: Martin Kepplinger
---
Please review this by looking at the driver too. Thanks,
martin
Documentatio
Sorry for the lack of version prefix in the title. This patchset should be
version 2.
On Mon, Apr 02, 2018 at 08:31:22PM +0800, Alan Kao wrote:
> This implements the baseline PMU for RISC-V platforms.
>
> To ease future PMU portings, a guide is also written, containing
> perf concepts, arch port
Cc: Nick Hu
Cc: Greentime Hu
Signed-off-by: Alan Kao
---
Documentation/riscv/pmu.txt | 249
1 file changed, 249 insertions(+)
create mode 100644 Documentation/riscv/pmu.txt
diff --git a/Documentation/riscv/pmu.txt b/Documentation/riscv/pmu.txt
new
This patch provide a basic PMU, riscv_base_pmu, which supports two
general hardware event, instructions and cycles. Furthermore, this
PMU serves as a reference implementation to ease the portings in
the future.
riscv_base_pmu should be able to run on any RISC-V machine that
conforms to the Priv-S
This implements the baseline PMU for RISC-V platforms.
To ease future PMU portings, a guide is also written, containing
perf concepts, arch porting practices and some hints.
Changes in v2:
- Fix the bug reported by Alex, which was caused by not sufficient
initialization. Check https://lkml.o
From: Andrey Ryabinin
Functions like memset/memmove/memcpy do a lot of memory accesses.
If bad pointer passed to one of these function it is important
to catch this. Compiler's instrumentation cannot do this since
these functions are written in assembly.
KASan replaces memory functions with manu
From: Andrey Ryabinin
This patch initializes KASan shadow region's page table and memory.
There are two stage for KASan initializing:
1. At early boot stage the whole shadow region is mapped to just
one physical page (kasan_zero_page). It's finished by the function
kasan_early_init which is
From: Andrey Ryabinin
Disable instrumentation for arch/arm/boot/compressed/*
,arch/arm/kvm/hyp/* and arch/arm/vdso/* because those
code won't linkd with kernel image.
Disable kasan check in the function unwind_pop_register
because it doesn't matter that kasan checks failed when
unwind_pop_regist
The purpose of this patch is to provide set_ttbr0/get_ttbr0
to kasan_init function. The definitions of cp15 registers
should be in arch/arm/include/asm/cp15.h rather than
arch/arm/include/asm/kvm_hyp.h, so move them.
Cc: Andrey Ryabinin
Reviewed-by: Marc Zyngier
Reviewed-by: Russell King - ARM L
From: Andrey Ryabinin
This patch enable kernel address sanitizer for arm.
Cc: Andrey Ryabinin
Acked-by: Dmitry Vyukov
Tested-by: Joel Stanley
Tested-by: Florian Fainelli
Tested-by: Abbott Liu
Signed-off-by: Abbott Liu
---
Documentation/dev-tools/kasan.rst | 2 +-
arch/arm/Kconfig
From: Andrey Ryabinin
Changelog:
v3 - v2
- Remove this patch: 2 1-byte checks more safer for memory_is_poisoned_16
because a unaligned load/store of 16 bytes is rare on arm, and this
patch is very likely to affect the performance of modern CPUs.
---Acked by: Russell King - ARM Linux
- Fixe
Define KASAN_SHADOW_OFFSET,KASAN_SHADOW_START and KASAN_SHADOW_END for arm
kernel address sanitizer.
++ 0x
||
||
||
++ CONFIG_PAGE_OFFSET
|| || |-> module virtual address space area.
||/
++ MODULE_VADDR = KASA
This extends the sysfs interface for thermal cooling devices and exposes
some pretty useful statistics. These statistics have proven to be quite
useful specially while doing benchmarks related to the task scheduler,
where we want to make sure that nothing has disrupted the test,
specially the cooli
Hi Alex,
On Mon, Apr 02, 2018 at 03:36:12PM +0800, Alan Kao wrote:
> On Sat, Mar 31, 2018 at 03:47:10PM -0700, Alex Solomatnikov wrote:
>
> The original guess was that maybe, an counter value on a hart is picked
> as the minusend, and an old counter value on another hart was recorded
> as the s
On Sat, Mar 31, 2018 at 03:47:10PM -0700, Alex Solomatnikov wrote:
The original guess was that maybe, an counter value on a hart is picked
as the minusend, and an old counter value on another hart was recorded
as the subtrahend but numerically larger. Then, the overflow causes
by that subtractio
On 28-03-18, 22:59, Sanjeev Gupta wrote:
> All links working.
And why is it important to convert them to https ?
> Signed-off-by: Sanjeev Gupta
> ---
> Documentation/thermal/cpu-cooling-api.txt | 2 +-
> Documentation/thermal/nouveau_thermal | 2 +-
> 2 files changed, 2 insertions(+), 2 del
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