Sphinx 1.6 generates some LaTeX code before each table,
starting its own environment before calling tabulary,
apparently to improve table layout.
The problem is that such environment is incompatible with
adjustbox. While, in thesis, it should be possible to override
it or to redefine tabulary, I w
On Tue, Aug 22, 2017 at 01:14:09PM +0800, icen...@aosc.io wrote:
> 在 2017-08-21 17:34，Maxime Ripard 写道：
> > Hi,
> >
> > On Sun, Aug 20, 2017 at 01:29:57PM +0800, Icenowy Zheng wrote:
> > > Allwinner R40 is a new SoC, with Quad Core Cortex-A7 and peripherals
> > > like A20.
> > >
> > > Add support
Signed-off-by: Alexander Kuleshov
---
lib/assoc_array.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/lib/assoc_array.c b/lib/assoc_array.c
index 59fd7c0b119c..155c55d8db5f 100644
--- a/lib/assoc_array.c
+++ b/lib/assoc_array.c
@@ -1,6 +1,6 @@
/* Generic associative array i
On Sat, Aug 19, 2017 at 02:09:58PM -0500, Eric W. Biederman wrote:
> Ram Pai writes:
>
> > diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c
> > index d4e545d..fe1e7c7 100644
> > --- a/arch/powerpc/kernel/traps.c
> > +++ b/arch/powerpc/kernel/traps.c
> > @@ -20,6 +20,7 @@
> >
On Tue, Aug 22, 2017 at 11:35:20PM +0800, Anand Jain wrote:
> >>
> >> I think AE is the only good solution for this, File-name encryption at
> >>this stage won't solve any kind of Evil Maid attack, (as it was quoted
> >>somewhere else in ML).
> >>
> >>
> >> Further, below, is define but not use
On Tue, Aug 22, 2017 at 11:33:51PM +0800, Anand Jain wrote:
>
>
> On 08/22/2017 10:55 AM, Eric Biggers wrote:
> >On Tue, Aug 22, 2017 at 10:22:30AM +0800, Anand Jain wrote:
> >>
> >>Hi Eric,
> >>
> >> How about a section on the threat model specific to the file-name ?
> >>
> >> (Sorry if I am
On Mon, Aug 14, 2017 at 07:32:09PM +0100, Roman Gushchin wrote:
> @@ -817,67 +817,12 @@ static bool task_will_free_mem(struct task_struct *task)
> return ret;
> }
>
> -static void oom_kill_process(struct oom_control *oc, const char *message)
> +static void __oom_kill_process(struct task_st
Hi Roman,
great work! This looks mostly good to me now. Below are some nitpicks
concerning naming and code layout, but nothing major.
On Mon, Aug 14, 2017 at 07:32:11PM +0100, Roman Gushchin wrote:
> @@ -39,6 +39,7 @@ struct oom_control {
> unsigned long totalpages;
> struct task_stru
There is no need to use rng-tools for feeding random data into kernel
entropy pool as hw_random core handles it. Documentation suggested that
rng-tools is required which is incorrect. So remove it.
Signed-off-by: PrasannaKumar Muralidharan
---
Documentation/hw_random.txt | 4
1 file changed
+fscrypt is not guaranteed to protect confidentiality or authenticity
+if an attacker is able to manipulate the filesystem offline prior to
+an authorized user later accessing the filesystem.
How does fscrypt / Android protect against Evil Maid attack. ?
_However_, an "Evil Maid" attacke
On 08/22/2017 10:55 AM, Eric Biggers wrote:
On Tue, Aug 22, 2017 at 10:22:30AM +0800, Anand Jain wrote:
Hi Eric,
How about a section on the threat model specific to the file-name ?
(Sorry if I am missing something).
Thanks, Anand
It's already mentioned that filenames are encrypted:
On 08/22/2017 10:23 AM, Petr Mladek wrote:
> On Tue 2017-08-22 10:09:40, Prarit Bhargava wrote:
>>
>>
>> On 08/17/2017 11:30 AM, Mark Salyzyn wrote:
>>> On 08/17/2017 06:15 AM, Prarit Bhargava wrote:
printk.time=1/CONFIG_PRINTK_TIME=1 adds a unmodified local hardware clock
timestamp to
On Tue 2017-08-22 10:09:40, Prarit Bhargava wrote:
>
>
> On 08/17/2017 11:30 AM, Mark Salyzyn wrote:
> > On 08/17/2017 06:15 AM, Prarit Bhargava wrote:
> >> printk.time=1/CONFIG_PRINTK_TIME=1 adds a unmodified local hardware clock
> >> timestamp to printk messages. The local hardware clock loses
On 08/17/2017 11:30 AM, Mark Salyzyn wrote:
> On 08/17/2017 06:15 AM, Prarit Bhargava wrote:
>> printk.time=1/CONFIG_PRINTK_TIME=1 adds a unmodified local hardware clock
>> timestamp to printk messages. The local hardware clock loses time each
>> day making it difficult to determine exactly when
On 22.08.2017 15:24, Benjamin Gaignard wrote:
> 2017-08-22 14:11 GMT+02:00 m18063 :
>> Hi Thierry,
>>
>> I added few other comments below. Please let me know what you think.
>>
>> Thank you,
>> Claudiu
>>
>> On 21.08.2017 14:25, Thierry Reding wrote:
>>> On Mon, Aug 21, 2017 at 01:23:08PM +0300,
2017-08-22 14:11 GMT+02:00 m18063 :
> Hi Thierry,
>
> I added few other comments below. Please let me know what you think.
>
> Thank you,
> Claudiu
>
> On 21.08.2017 14:25, Thierry Reding wrote:
>> On Mon, Aug 21, 2017 at 01:23:08PM +0300, m18063 wrote:
>>> Hi Thierry,
>>>
>>> Thank you for your re
Hi Thierry,
I added few other comments below. Please let me know what you think.
Thank you,
Claudiu
On 21.08.2017 14:25, Thierry Reding wrote:
> On Mon, Aug 21, 2017 at 01:23:08PM +0300, m18063 wrote:
>> Hi Thierry,
>>
>> Thank you for your response. I added few comments below.
>>
>> Thank you,
This patchset adds support for HiSilicon SoC uncore PMUs driver. It
includes L3C, Hydra Home Agent (HHA) and DDRC.
Changes in v5:
* remove unnecessary name/num_events member in hisi_pmu
* refactor hisi_pmu_hwevents structure
* remove hisi_pmu_alloc function
* revise cpuhotplug for L3C PMUs
* add c
L3 cache coherence is maintained by Hydra Home Agent (HHA) in HiSilicon
SoC. This patch adds support for HHA PMU driver, Each HHA has own
control, counter and interrupt registers and is an separate PMU. For
each HHA PMU, it has 16-programable counters and each counter is
free-running. Interrupt is
This patch adds documentation for the uncore PMUs on HiSilicon SoC.
Reviewed-by: Jonathan Cameron
Signed-off-by: Shaokun Zhang
Signed-off-by: Anurup M
---
Documentation/perf/hisi-pmu.txt | 53 +
1 file changed, 53 insertions(+)
create mode 100644 Docume
Add support HiSilicon SoC uncore PMU driver.
Signed-off-by: Shaokun Zhang
---
MAINTAINERS | 7 +++
1 file changed, 7 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 1c3feff..9d1ad57 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -6147,6 +6147,13 @@ S: Maintained
F: driv
This patch adds support for L3C PMU driver in HiSilicon SoC chip, Each
L3C has own control, counter and interrupt registers and is an separate
PMU. For each L3C PMU, it has 8-programable counters and each counter
is free-running. Interrupt is supported to handle counter (48-bits)
overflow.
Reviewe
This patch adds support for DDRC PMU driver in HiSilicon SoC chip, Each
DDRC has own control, counter and interrupt registers and is an separate
PMU. For each DDRC PMU, it has 8-fixed-purpose counters which have been
mapped to 8-events by hardware, it assumes that counter index is equal
to event co
This patch adds support HiSilicon SoC uncore PMU driver framework and
interfaces.
Reviewed-by: Jonathan Cameron
Signed-off-by: Shaokun Zhang
Signed-off-by: Anurup M
---
drivers/perf/Kconfig | 7 +
drivers/perf/Makefile| 1 +
drivers/perf/hisilicon/Ma
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