On Tue, Jul 18, 2017 at 12:59 PM, Jintack Lim wrote:
> Forward ELR_EL1, SPSR_EL1 and VBAR_EL1 traps to the virtual EL2 if the
> virtual HCR_EL2.NV bit is set.
>
> This is for recursive nested virtualization.
>
> Signed-off-by: Jintack Lim
This should be linaro e-mail address. Will fix it.
> ---
On Tue, Jul 18, 2017 at 12:58 PM, Jintack Lim wrote:
> Nested virtualization is the ability to run a virtual machine inside another
> virtual machine. In other words, it’s about running a hypervisor (the guest
> hypervisor) on top of another hypervisor (the host hypervisor).
>
> Supporting nested
Add a new kernel parameter(kvm-arm.nested) to enable KVM/ARM nested
virtualization support. This kernel parameter on arm architecture is
ignored since nested virtualization is not supported on arm.
Note that this kernel parameter will not have any impact until nested
virtualization support is comp
Add a new ARM64_HAS_NESTED_VIRT feature to indicate that the
CPU has the ARMv8.3 nested virtualization capability.
This will be used to support nested virtualization in KVM.
Signed-off-by: Jintack Lim
---
arch/arm64/include/asm/cpucaps.h | 3 ++-
arch/arm64/include/asm/sysreg.h | 1 +
arch/a
Nested virtualization is the ability to run a virtual machine inside another
virtual machine. In other words, it’s about running a hypervisor (the guest
hypervisor) on top of another hypervisor (the host hypervisor).
Supporting nested virtualization on ARM means that the hypervisor provides not
on
Nested virtualizaion is in use only if all three conditions are met:
- The architecture supports nested virtualization.
- The kernel parameter is set.
- The userspace uses nested virtualiztion feature.
Signed-off-by: Jintack Lim
---
arch/arm/include/asm/kvm_host.h | 11 +++
arch/arm64/
From: Christoffer Dall
Set the initial exception level of the guest to EL2 if nested
virtualization feature is enabled.
Signed-off-by: Christoffer Dall
Signed-off-by: Jintack Lim
---
arch/arm64/include/asm/kvm_host.h | 2 +-
arch/arm64/include/uapi/asm/kvm.h | 1 +
arch/arm64/kvm/reset.c
From: Christoffer Dall
We were not allowing userspace to set a more privileged mode for the VCPU
than EL1, but now that we support nesting with a virtual EL2 mode, do
allow this!
Signed-off-by: Christoffer Dall
---
arch/arm64/kvm/guest.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/ar
ARM v8.3 introduces a new bit in the HCR_EL2, which is the NV bit. When
this bit is set, accessing EL2 registers in EL1 traps to EL2. In
addition, executing the following instructions in EL1 will trap to EL2:
tlbi, at, eret, and msr/mrs instructions to access SP_EL1. Most of the
instructions that t
From: Christoffer Dall
When running a nested hypervisor we occasionally have to figure out if
the mode we are switching into is the virtual EL2 mode or a regular
EL0/1 mode.
Signed-off-by: Christoffer Dall
---
arch/arm/include/asm/kvm_emulate.h | 6 ++
arch/arm64/include/asm/kvm_emulate
If the guest exception level is EL2, then set up the shadow context of
the virtual EL2 to hardware. Otherwise, set the regular EL0/EL1 context.
Note that the shadow context content will be prepared in subsequent
patches.
Signed-off-by: Jintack Lim
---
arch/arm64/kvm/context.c | 74 +
From: Christoffer Dall
Add functions setting up and restoring the guest's context on each entry
and exit. These functions will come in handy when we want to use
different context for normal EL0/EL1 and virtual EL2 execution.
No functional change yet.
Signed-off-by: Christoffer Dall
Signed-off-
With the nested virtualization support, a hypervisor running inside a VM
(i.e. a guest hypervisor) is now deprivilaged and runs in EL1 instead of
EL2. So, the host hypervisor manages the shadow context for the virtual
EL2 execution.
Signed-off-by: Jintack Lim
---
arch/arm64/include/asm/kvm_host.
From: Christoffer Dall
Some bits of the TCR weren't defined and since we're about to use these
in KVM, add these defines.
Signed-off-by: Christoffer Dall
---
arch/arm64/include/asm/pgtable-hwdef.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/include/asm/pgtable-hwdef.h
To support the virtual EL2 execution, we need to maintain the EL2
special registers such as SPSR_EL2, ELR_EL2 and SP_EL2 in vcpu context.
Note that SP_EL2 is not accessible in EL2, so we don't need a trap
handler for this register.
Signed-off-by: Jintack Lim
---
arch/arm64/include/asm/kvm_host.
From: Christoffer Dall
When running in virtual EL2 mode, we actually run the hardware in EL1
and therefore have to use the EL1 registers to ensure correct operation.
By setting the HCR.TVM and HCR.TVRM we ensure that the virtual EL2 mode
doesn't shoot itself in the foot when setting up what it b
From: Christoffer Dall
When entering virtual EL2, we need to reflect virtual EL2 register
states to corresponding shadow EL1 registers. We can simply copy them if
their formats are identical. Otherwise, we need to convert EL2 register
state to EL1 register state.
When entering EL1/EL0, we need
Support inject synchronous exceptions to the virtual EL2 as
described in ARM ARM AArch64.TakeException().
This can be easily extended to support to inject asynchronous exceptions
to the virtual EL2, but it will be added in a later patch when appropriate.
Signed-off-by: Jintack Lim
---
arch/arm/
These macros and enums can be reused to inject exceptions
for nested virtualization.
Signed-off-by: Jintack Lim
---
arch/arm64/include/asm/kvm_emulate.h | 12
arch/arm64/kvm/inject_fault.c| 12
2 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/arc
For the same reason we trap virtual memory register accesses at virtual
EL2, we need to trap SPSR_EL1, ELR_EL1 and VBAR_EL1 accesses. ARM v8.3
introduces the HCR_EL2.NV1 bit to be able to trap on those register
accesses in EL1. Do not set this bit until the whole nesting support is
completed.
Sign
When running in virtual EL2 we use the shadow EL1 systerm register array
for the save/restore process, so that hardware and especially the memory
subsystem behaves as code written for EL2 expects while really running
in EL1.
This works great for EL1 system register accesses that we trap, because
t
VMs used to execute hvc #0 for the psci call if EL3 is not implemented.
However, when we come to provide the virtual EL2 mode to the VM, the
host OS inside the VM calls kvm_call_hyp() which is also hvc #0. So,
it's hard to differentiate between them from the host hypervisor's point
of view.
So, le
When HCR.NV bit is set, eret instructions trap to EL2 with EC code 0x1A.
Emulate eret instructions by setting pc and pstate.
Note that the current exception level is always the virtual EL2, since
we set HCR_EL2.NV bit only when entering the virtual EL2. So, we take
spsr and elr states from the vir
For the same reason we trap virtual memory register accesses in virtual
EL2, we trap CPACR_EL1 access too; We allow the virtual EL2 mode to
access EL1 system register state instead of the virtual EL2 one.
Signed-off-by: Jintack Lim
---
arch/arm64/kvm/hyp/switch.c | 10 +++---
arch/arm64/kvm/
When HCR.NV bit is set, execution of the EL2 translation regime address
aranslation instructions and TLB maintenance instructions are trapped to
EL2. In addition, execution of the EL1 translation regime address
aranslation instructions and TLB maintenance instructions that are only
accessible from
Now that the psci call is done by the smc instruction when nested
virtualization is enabled, it is clear that all hvc instruction from the
VM (including from the virtual EL2) are supposed to handled in the
virtual EL2.
Signed-off-by: Jintack Lim
---
arch/arm64/kvm/handle_exit.c | 6 ++
1 fil
Forward exceptions due to WFI or WFE instructions to the virtual EL2 if
they are not coming from the virtual EL2 and virtual HCR_EL2.TWX is set.
Signed-off-by: Jintack Lim
---
arch/arm64/include/asm/kvm_host.h | 1 +
arch/arm64/kvm/handle_exit.c | 13 -
arch/arm64/kvm/nested.c
ARMv8.1 added more EL2 registers: TTBR1_EL2, CONTEXTIDR_EL2, and three
EL2 virtual timer registers. Add the first two registers to vcpu context
and set their handlers. The timer registers and their handlers will be
added in a separate patch.
Signed-off-by: Jintack Lim
---
arch/arm64/include/asm/
These macros will be used to support the virtual EL2 with VHE.
Signed-off-by: Jintack Lim
---
arch/arm64/include/asm/kvm_emulate.h | 24
1 file changed, 24 insertions(+)
diff --git a/arch/arm64/include/asm/kvm_emulate.h
b/arch/arm64/include/asm/kvm_emulate.h
index 3017
On VHE systems, EL0 of the host kernel is considered as a part of 'VHE
host'; The execution of EL0 is affected by system registers set by the
VHE kernel including the hypervisor. To emulate this for a VM, we use
the same set of system registers (i.e. shadow registers) for the virtual
EL2 and EL0 ex
When creating the shadow context for the virtual EL2 execution, we can
directly copy the EL2 register states to the shadow EL1 register states
if the virtual HCR_EL2.E2H bit is set. This is because EL1 and EL2
system register formats compatible with E2H=1.
Now that we allow the virtual EL2 modify
Forward traps due to FP/ASIMD register accesses to the virtual EL2 if
virtual CPTR_EL2.TFP is set. Note that if TFP bit is set, then even
accesses to FP/ASIMD register from EL2 as well as NS EL0/1 will trap to
EL2. So, we don't check the VM's exception level.
Signed-off-by: Jintack Lim
---
arch/
When the virtual E2H bit is set, we can support EL2 register accesses
via EL1 registers from the virtual EL2 by doing trap-and-emulate. A
better alternative, however, is to allow the virtual EL2 to access EL2
register states without trap. This can be easily achieved by not traping
EL1 registers sin
Now that the virtual EL2 can access EL2 register states via EL1
registers, we need to consider it when selecting the register to
emulate.
Signed-off-by: Jintack Lim
---
arch/arm64/kvm/sys_regs.c | 46 --
1 file changed, 44 insertions(+), 2 deletions(-)
While the EL1 virtual memory control registers can be accessed in the
virtual EL2 with VHE without trap to manuplate the virtual EL2 states,
we can't do that for CPTR_EL2 for an unfortunate reason.
This is because the top bit of CPTR_EL2, which is TCPAC, will be ignored
if it is accessed via CPACR
With HCR_EL2.NV bit set, accesses to EL12 registers in the virtual EL2
trap to EL2. Handle those traps just like we do for EL1 registers.
One exception is CNTKCTL_EL12. We don't trap on CNTKCTL_EL1 for non-VHE
virtual EL2 because we don't have to. However, accessing CNTKCTL_EL12
will trap since it
Forward traps due to HCR_EL2.NV bit to the virtual EL2 if they are not
coming from the virtual EL2 and the virtual HCR_EL2.NV bit is set.
This is for recursive nested virtualization.
Signed-off-by: Jintack Lim
---
arch/arm64/include/asm/kvm_arm.h| 1 +
arch/arm64/include/asm/kvm_coproc.h |
Forward the EL1 virtual memory register traps to the virtual EL2 if they
are not coming from the virtual EL2 and the virtual HCR_EL2.TVM or TRVM
bit is set.
This is for recursive nested virtualization.
Signed-off-by: Jintack Lim
---
arch/arm64/kvm/sys_regs.c | 24
1 fil
In addition to EL2 register accesses, setting NV bit will also make EL12
register accesses trap to EL2. To emulate this for the virtual EL2,
forword traps due to EL12 register accessses to the virtual EL2 if the
virtual HCR_EL2.NV bit is set.
This is for recursive nested virtualization.
Signed-of
Forward CPACR_EL1 traps to the virtual EL2 if virtual CPTR_EL2 is
configured to trap CPACR_EL1 accesses from EL1.
This is for recursive nested virtualization.
Signed-off-by: Jintack Lim
---
arch/arm64/kvm/sys_regs.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/kvm/sys_reg
Forward ELR_EL1, SPSR_EL1 and VBAR_EL1 traps to the virtual EL2 if the
virtual HCR_EL2.NV bit is set.
This is for recursive nested virtualization.
Signed-off-by: Jintack Lim
---
arch/arm64/include/asm/kvm_arm.h | 1 +
arch/arm64/kvm/sys_regs.c| 18 ++
2 files changed, 1
On 07/17/2017 06:39 AM, Geert Uytterhoeven wrote:
> All low-level PM/SMP code using virt_to_phys() should actually use
> __pa_symbol() against kernel symbols. Update the documentation to move
> away from virt_to_phys().
>
> Cfr. commit 6996cbb2372189f7 ("ARM: 8641/1: treewide: Replace uses of
> v
Attention:Beneficiary
I am Meliana Trump, and I am writing to inform you about your Bank
Check Draft brought back 16/07/2017 by the United Embassy Mr John
Moore from the government of Benin Republic in the white house
Washington DC been mandated to be deliver to your home address once
you reconfi
On 7/18/2017 7:03 AM, Thomas Gleixner wrote:
On Mon, 17 Jul 2017, Tom Lendacky wrote:
This patch series provides support for AMD's new Secure Memory Encryption (SME)
feature.
SME can be used to mark individual pages of memory as encrypted through the
page tables. A page of memory that is marked
On 7/18/2017 4:36 AM, Ingo Molnar wrote:
* Tom Lendacky wrote:
Create a new function attribute, __nostackp, that can used to turn off
stack protection on a per function basis.
Signed-off-by: Tom Lendacky
---
include/linux/compiler-gcc.h | 2 ++
include/linux/compiler.h | 4
2 f
On Tue, 18 Jul 2017 08:42:42 +0200
Daniel Vetter wrote:
> > Commit 8f2e045ec878 (drm/color: un-inline drm_color_lut_extract()) moved
> > the only kerneldoc comment out of include/drm/drm_color_mgmt.h, leading to
> > this warning:
> >
> > ./include/drm/drm_color_mgmt.h:1: warning: no structur
On Mon, 17 Jul 2017, Tom Lendacky wrote:
> This patch series provides support for AMD's new Secure Memory Encryption
> (SME)
> feature.
>
> SME can be used to mark individual pages of memory as encrypted through the
> page tables. A page of memory that is marked encrypted will be automatically
>
* Tom Lendacky wrote:
> Create a new function attribute, __nostackp, that can used to turn off
> stack protection on a per function basis.
>
> Signed-off-by: Tom Lendacky
> ---
> include/linux/compiler-gcc.h | 2 ++
> include/linux/compiler.h | 4
> 2 files changed, 6 insertions(+)
>
> Am 17.07.2017 um 12:57 schrieb Mauro Carvalho Chehab
> :
>
> So, we need a way for kfigure to fallback when distros don't
> have such feature.
Hm .. I'am not very happy to implement where distros packaging fail.
But .. if there is really a need for, I will do so.
Lets see how this series goe
This patch adds documentation for the uncore PMUs on HiSilicon SoC.
Signed-off-by: Shaokun Zhang
Signed-off-by: Anurup M
---
Documentation/perf/hisi-pmu.txt | 51 +
1 file changed, 51 insertions(+)
create mode 100644 Documentation/perf/hisi-pmu.txt
diff
This patch adds support HiSilicon SoC uncore PMU driver framework and
interfaces.
Signed-off-by: Shaokun Zhang
Signed-off-by: Anurup M
---
drivers/perf/Kconfig | 7 +
drivers/perf/Makefile| 1 +
drivers/perf/hisilicon/Makefile | 1 +
driver
This patchset adds support for HiSilicon SoC uncore PMUs driver. It
includes L3C, Hydra Home Agent (HHA) and DDRC.
Changes in v3:
* rebase to 4.13-rc1
* add dev_err if ioremap fails for PMUs
Changes in v2:
* fix kbuild test robot error
* make hisi_uncore_ops static
Shaokun Zhang (6):
Document
L3 cache coherence is maintained by Hydra Home Agent (HHA) in HiSilicon
SoC. This patch adds support for HHA PMU driver, Each HHA has own
control, counter and interrupt registers and is an separate PMU. For
each HHA PMU, it has 16-programable counters and supports 0x50 events,
event code is 8-bits
This patch adds support for L3C PMU driver in HiSilicon SoC chip, Each
L3C has own control, counter and interrupt registers and is an separate
PMU. For each L3C PMU, it has 8-programable counters and supports 0x60
events, event code is 8-bits and every counter is free-running.
Interrupt is supporte
This patch adds support for DDRC PMU driver in HiSilicon SoC chip, Each
DDRC has own control, counter and interrupt registers and is an separate
PMU. For each DDRC PMU, it has 8-fixed-purpose counters which have been
mapped to 8-events by hardware, it assumes that counter index is equal
to event co
Add support HiSilicon SoC uncore PMU driver.
Signed-off-by: Shaokun Zhang
---
MAINTAINERS | 7 +++
1 file changed, 7 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 205d397..649b144 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -6197,6 +6197,13 @@ S: Maintained
F: driv
Hi Russell,
On Mon, Jul 17, 2017 at 11:20 PM, Russell King - ARM Linux
wrote:
> On Mon, Jul 17, 2017 at 01:44:45PM -0600, Jonathan Corbet wrote:
>> On Mon, 17 Jul 2017 15:39:28 +0200
>> Geert Uytterhoeven wrote:
>>
>> > All low-level PM/SMP code using virt_to_phys() should actually use
>> > __pa
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