On Thu, May 4, 2017 at 9:49 PM, Icenowy Zheng wrote:
> From: Icenowy Zheng
Do you want to update your author email address?
>
> Allwinner R40 is a new SoC, with Quad Core Cortex-A7 and peripherals
> like A20.
>
> Add support for it.
>
> Signed-off-by: Icenowy Zheng
Same here.
For the subject
On Thu, May 04, 2017 at 09:34:09AM -0500, Tom Lendacky wrote:
> I masked it out here based on a previous comment from Dave Hansen:
>
> http://marc.info/?l=linux-kernel&m=148778719826905&w=2
>
> I could move the __sme_clr into the individual defines of:
Nah, it is fine as it is. I was just wond
From: Icenowy Zheng
Allwinner R40 is a new SoC, with Quad Core Cortex-A7 and peripherals
like A20.
Add support for it.
Signed-off-by: Icenowy Zheng
---
Documentation/arm/sunxi/README | 4
Documentation/devicetree/bindings/arm/sunxi.txt | 1 +
arch/arm/mach-sunxi/sunxi.c
From: Icenowy Zheng
Allwinner R40 SoC have a clock controller module in the style of the
SoCs beyond sun6i, however, it's more rich and complex.
Add support for it.
Signed-off-by: Icenowy Zheng
---
Changes in v2:
- Fixes according to the SoC's user manual.
drivers/clk/sunxi-ng/Kconfig
Allwinner R40 has a clock controlling unit like the ones on other
Allwinner SoCs after sun6i, and can also use a CCU-based driver.
Add a compatible string for it.
Signed-off-by: Icenowy Zheng
---
Documentation/devicetree/bindings/clock/sunxi-ccu.txt | 1 +
1 file changed, 1 insertion(+)
diff -
R40 is said to be an upgrade of A20, and its pin configuration is also
similar to A20 (and thus similar to A10).
Add support for R40 to the A10 pinctrl driver.
Signed-off-by: Icenowy Zheng
---
drivers/pinctrl/sunxi/Kconfig | 2 +-
drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c | 272 ++
Allwinner R40 has a pin controller like the ones in older Allwinner SoCs
(especially A20), and can use modified version of the A10/A20 pinctrl
driver.
Add a compatible string for it.
Signed-off-by: Icenowy Zheng
---
Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 1 +
1
As we added A20 support to A10 pinctrl driver, now we can delete the
dedicated A20 pinctrl driver, and enable A10 driver for A20.
Signed-off-by: Icenowy Zheng
---
drivers/pinctrl/sunxi/Kconfig |6 +-
drivers/pinctrl/sunxi/Makefile|1 -
drivers/pinctrl/sunxi/pinctr
From: Chen-Yu Tsai
The Allwinner R40 SoC is marketed as the successor to the A20 SoC.
The R40 is a smaller chip than the A20, but features the same set
of programmable pins, with a couple extra pins and some new pin
functions. The chip features 4 Cortex-A7 cores and a Mali-400 MP2
GPU. It retains
On 4/27/2017 11:12 AM, Borislav Petkov wrote:
On Tue, Apr 18, 2017 at 04:17:54PM -0500, Tom Lendacky wrote:
Changes to the existing page table macros will allow the SME support to
be enabled in a simple fashion with minimal changes to files that use these
macros. Since the memory encryption m
On Thu, May 04, 2017 at 09:50:05PM +0800, Icenowy Zheng wrote:
> From: Chen-Yu Tsai
>
> The Allwinner R40 SoC is marketed as the successor to the A20 SoC.
> The R40 is a smaller chip than the A20, but features the same set
> of programmable pins, with a couple extra pins and some new pin
> functi
On Thu, May 04, 2017 at 10:07:47PM +0800, Icenowy Zheng wrote:
>
>
> 于 2017年5月4日 GMT+08:00 下午10:04:31, Maxime Ripard
> 写到:
> >On Thu, May 04, 2017 at 09:49:58PM +0800, Icenowy Zheng wrote:
> >> Allwinner A10, A20 and R40 SoCs have similar GPIO layout.
> >>
> >> Add SoC definitions in pinctrl-s
On Thu, May 04, 2017 at 09:50:06PM +0800, Icenowy Zheng wrote:
> From: Chen-Yu Tsai
>
> The Banana Pi M2 Ultra is an SBC based on the Allwinner R40 SoC. The
> form factor and position of various connectors, leds and buttons is
> similar to the Banana Pi M1+, Banana Pi M3, and is exactly the same
On 5/4/2017 5:16 AM, Borislav Petkov wrote:
On Tue, Apr 18, 2017 at 04:18:22PM -0500, Tom Lendacky wrote:
The boot data and command line data are present in memory in a decrypted
state and are copied early in the boot process. The early page fault
support will map these areas as encrypted, so b
于 2017年5月4日 GMT+08:00 下午10:41:52, Maxime Ripard
写到:
>On Thu, May 04, 2017 at 10:03:26PM +0800, Icenowy Zheng wrote:
>>
>>
>> 于 2017年5月4日 GMT+08:00 下午10:02:20, Maxime Ripard
> 写到:
>> >On Thu, May 04, 2017 at 09:49:59PM +0800, Icenowy Zheng wrote:
>> >> static const struct of_device_id sun4i_a
On Thu, May 04, 2017 at 10:03:26PM +0800, Icenowy Zheng wrote:
>
>
> 于 2017年5月4日 GMT+08:00 下午10:02:20, Maxime Ripard
> 写到:
> >On Thu, May 04, 2017 at 09:49:59PM +0800, Icenowy Zheng wrote:
> >> static const struct of_device_id sun4i_a10_pinctrl_match[] = {
> >> - { .compatible = "allwinner,su
On Thu, May 04, 2017 at 09:24:11AM -0500, Tom Lendacky wrote:
> I did this so that an the include order wouldn't cause issues (including
> asm/mem_encrypt.h followed by later by a linux/mem_encrypt.h include).
> I can make this a bit clearer by having separate #defines for each
> thing, e.g.:
>
>
On 4/27/2017 10:46 AM, Borislav Petkov wrote:
On Tue, Apr 18, 2017 at 04:17:27PM -0500, Tom Lendacky wrote:
Add support for Secure Memory Encryption (SME). This initial support
provides a Kconfig entry to build the SME support into the kernel and
defines the memory encryption mask that will be u
On Thu, May 04, 2017 at 09:50:04PM +0800, Icenowy Zheng wrote:
> From: Icenowy Zheng
>
> Allwinner R40 SoC have a clock controller module in the style of the
> SoCs beyond sun6i, however, it's more rich and complex.
>
> Add support for it.
>
> Signed-off-by: Icenowy Zheng
> ---
> Changes in v2
As A20 is designed as a pin-compatible upgrade of A10, their pin
controller are very similar, and can share one driver.
Add A20 support to the A10 driver.
Signed-off-by: Icenowy Zheng
---
drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c | 287 +++---
1 file changed, 224 inserti
Allwinner A10, A20 and R40 SoCs have similar GPIO layout.
Add SoC definitions in pinctrl-sunxi.h, in order to merge A20 support
into A10 driver, and add R40 support into it.
Signed-off-by: Icenowy Zheng
---
drivers/pinctrl/sunxi/pinctrl-sunxi.h | 3 +++
1 file changed, 3 insertions(+)
diff --g
On 4/27/2017 10:52 AM, Dave Hansen wrote:
On 04/27/2017 12:25 AM, Dave Young wrote:
On 04/21/17 at 02:55pm, Dave Hansen wrote:
On 04/18/2017 02:22 PM, Tom Lendacky wrote:
Add sysfs support for SME so that user-space utilities (kdump, etc.) can
determine if SME is active.
A new directory will
From: Chen-Yu Tsai
The Banana Pi M2 Ultra is an SBC based on the Allwinner R40 SoC. The
form factor and position of various connectors, leds and buttons is
similar to the Banana Pi M1+, Banana Pi M3, and is exactly the same
as the latest Banana Pi M64.
It features:
- X-Powers AXP221s PMIC con
On 4/27/2017 2:25 AM, Dave Young wrote:
On 04/21/17 at 02:55pm, Dave Hansen wrote:
On 04/18/2017 02:22 PM, Tom Lendacky wrote:
Add sysfs support for SME so that user-space utilities (kdump, etc.) can
determine if SME is active.
A new directory will be created:
/sys/kernel/mm/sme/
And two en
于 2017年5月4日 GMT+08:00 下午10:04:31, Maxime Ripard
写到:
>On Thu, May 04, 2017 at 09:49:58PM +0800, Icenowy Zheng wrote:
>> Allwinner A10, A20 and R40 SoCs have similar GPIO layout.
>>
>> Add SoC definitions in pinctrl-sunxi.h, in order to merge A20 support
>> into A10 driver, and add R40 support i
On Thu, May 04, 2017 at 09:49:58PM +0800, Icenowy Zheng wrote:
> Allwinner A10, A20 and R40 SoCs have similar GPIO layout.
>
> Add SoC definitions in pinctrl-sunxi.h, in order to merge A20 support
> into A10 driver, and add R40 support into it.
While your commit log is good, the commit title is m
On 05/03/2017 04:26 PM, Mickaël Salaün wrote:
> Hi,
>
> This third patch series make the seccomp/test_harness.h more generally
> available [1] and update the kselftest documentation with the Sphinx format.
> It
> also improve the Makefile of seccomp tests to take into account any
> kselftest_harn
于 2017年5月4日 GMT+08:00 下午10:02:20, Maxime Ripard
写到:
>On Thu, May 04, 2017 at 09:49:59PM +0800, Icenowy Zheng wrote:
>> static const struct of_device_id sun4i_a10_pinctrl_match[] = {
>> -{ .compatible = "allwinner,sun4i-a10-pinctrl", },
>> +{
>> +.compatible = "allwinner,sun
On Thu, May 04, 2017 at 09:49:59PM +0800, Icenowy Zheng wrote:
> static const struct of_device_id sun4i_a10_pinctrl_match[] = {
> - { .compatible = "allwinner,sun4i-a10-pinctrl", },
> + {
> + .compatible = "allwinner,sun4i-a10-pinctrl",
> + .data = (void *)PINCTRL_S
This is the first non-RFC version of this patchset, which added basical
support including I2C, UART and MMC to the mainline Linux.
The pinctrl driver of A20 is also merged into the one of A10 before
R40 support is added into the A10 driver.
Chen-Yu Tsai (2):
ARM: dts: sun8i: Add basic dtsi file
Some more thoughts with your example, dmsetup might look like:
# dmsetup create --bootformat "lroot:uuid,rw,0 2097152 linear 8:2 0, \
2097152 2097152 linear 8:3 0, 4194304 2097152 linear 8:4 0"
- also supporting creating multiple devices if the semi-colon is used
- colon to separate name from uu
On Thu, May 04, 2017 at 01:18:41PM +0200, Enric Balletbo Serra wrote:
> I'm wondering if a command line like this would be acceptable.
1) Make sure the implementation continues to support backslash quoting
so that any characters you introduce with special meanings (comma,
semi-colon, double-quote
Mike,
2017-04-18 19:37 GMT+02:00 Kees Cook :
> On Tue, Apr 18, 2017 at 9:42 AM, Enric Balletbo i Serra
> wrote:
>> Hello,
>>
>> Some of these patches were send few years back, I saw that first
>> version was send to this list in 2010, and after version 4 did not
>> land [1]. Some days ago I resen
On Tue, Apr 18, 2017 at 04:18:22PM -0500, Tom Lendacky wrote:
> The boot data and command line data are present in memory in a decrypted
> state and are copied early in the boot process. The early page fault
> support will map these areas as encrypted, so before attempting to copy
> them, add decr
Hi Andre,
On jeu., mai 04 2017, Andre Przywara wrote:
> The Marvell Armada 3700 UART uses "ar3700_uart" for its earlycon name.
> Adjust documentation to match the code.
Actually I think it was the code which was wrong. But as it is already
part of the kernel it's too late to modify it.
>
> S
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