Fix typos in acpi directory to make documentation grammatically correct.
Signed-off-by: Tamara Diaconita
---
Documentation/acpi/aml-debugger.txt | 2 +-
Documentation/acpi/enumeration.txt | 6 +++---
Documentation/acpi/linuxized-acpica.txt | 6 +++---
3 files changed, 7 insertions(+), 7
,"Luis R . Rodriguez" ,Stanislaw Gruszka
,Peter Zijlstra ,Josh Poimboeuf
,Vitaly Kuznetsov ,Tim Chen
,Joerg Roedel
, TF-8?B?UmFkaW0gS3LEjW3DocWZ?From: h...@zytor.com
Message-ID: <550f6209-025a-45e2-84e2-f00a3771c...@zytor.com>
On March 14, 2017 2:20:19 PM PDT, Thomas Garnier wrote:
>On Tue, M
On Tue 2017-03-14 10:05:08, Thomas Garnier wrote:
> This patch makes the GDT remapped pages read-only to prevent corruption.
> This change is done only on 64-bit.
>
> The native_load_tr_desc function was adapted to correctly handle a
> read-only GDT. The LTR instruction always writes to the GDT TS
From: "Edward A. James"
This patchset adds a hwmon driver to support the OCC (On-Chip Controller)
on the IBM POWER8 and POWER9 processors, from a BMC (Baseboard Management
Controller). The OCC is an embedded processor that provides real time
power and thermal monitoring.
The driver provides an i
From: "Edward A. James"
Add core support for polling the OCC for it's sensor data and parsing
that data into sensor-specific information.
Signed-off-by: Edward A. James
Signed-off-by: Andrew Jeffery
---
Documentation/hwmon/occ| 42 +
MAINTAINERS| 7 +
drivers/hwmon/
From: "Edward A. James"
Add a generic mechanism to expose the sensors provided by the OCC in
sysfs.
Signed-off-by: Edward A. James
Signed-off-by: Andrew Jeffery
---
Documentation/hwmon/occ | 62 +++
drivers/hwmon/occ/Makefile| 2 +-
drivers/hwmon/occ/occ_sysfs.c | 253 +++
From: "Edward A. James"
Add code to tie the hwmon sysfs code and the POWER8 OCC code together,
as well as probe the entire driver from the I2C bus. I2C is the
communication method between the BMC and the P8 OCC.
Signed-off-by: Edward A. James
Signed-off-by: Andrew Jeffery
Acked-by: Rob Herring
From: "Edward A. James"
Add functions to parse the data structures that are specific to the OCC
on the POWER8 processor. These are the sensor data structures, including
temperature, frequency, power, and "caps."
Signed-off-by: Edward A. James
Signed-off-by: Andrew Jeffery
---
Documentation/hw
From: "Edward A. James"
Add functions to send SCOM operations over I2C bus. The BMC can
communicate with the Power8 host processor over I2C, but needs to use
SCOM operations in order to access the OCC register space.
Signed-off-by: Edward A. James
Signed-off-by: Andrew Jeffery
---
drivers/hwm
On Tue, Mar 14, 2017 at 11:06:52AM -0700, Hoan Tran wrote:
> This patch adds support for SoC-wide (AKA uncore) Performance Monitoring
> Unit in the next generation of X-Gene SoC.
>
> Signed-off-by: Hoan Tran
> ---
> drivers/perf/xgene_pmu.c | 645
> ++
On Tue, Mar 14, 2017 at 11:06:51AM -0700, Hoan Tran wrote:
> This patch adds support for SoC-wide (AKA uncore) Performance Monitoring
> Unit in the next generation of X-Gene SoC.
It adds a description, certainly.
>
> Signed-off-by: Hoan Tran
> ---
> Documentation/perf/xgene-pmu.txt | 17 ++
This patch set adds support for SoC-wide (AKA uncore) Performance Monitoring
Unit in the next generation of X-Gene SoC.
Hoan Tran (2):
Documentation: perf: xgene: Add support for SoC PMU of next generation of
X-Gene
perf: xgene: Add support for SoC PMU of next generation of X-Gene
Documenta
This patch adds support for SoC-wide (AKA uncore) Performance Monitoring
Unit in the next generation of X-Gene SoC.
Signed-off-by: Hoan Tran
---
Documentation/perf/xgene-pmu.txt | 17 +++--
1 file changed, 11 insertions(+), 6 deletions(-)
diff --git a/Documentation/perf/xgene-pmu.tx
This patch adds support for SoC-wide (AKA uncore) Performance Monitoring
Unit in the next generation of X-Gene SoC.
Signed-off-by: Hoan Tran
---
drivers/perf/xgene_pmu.c | 645 ++-
1 file changed, 575 insertions(+), 70 deletions(-)
diff --git a/driver
Each processor holds a GDT in its per-cpu structure. The sgdt
instruction gives the base address of the current GDT. This address can
be used to bypass KASLR memory randomization. With another bug, an
attacker could target other per-cpu structures or deduce the base of
the main memory section (PAGE
This patch makes the GDT remapped pages read-only to prevent corruption.
This change is done only on 64-bit.
The native_load_tr_desc function was adapted to correctly handle a
read-only GDT. The LTR instruction always writes to the GDT TSS entry.
This generates a page fault if the GDT is read-only
This patch aligns MODULES_END to the beginning of the Fixmap section.
It optimizes the space available for both sections. The address is
pre-computed based on the number of pages required by the Fixmap
section.
It will allow GDT remapping in the Fixmap section. The current
MODULES_END static addre
On Tue, Mar 14, 2017 at 02:58:24PM +0100, Radim Krčmář wrote:
> 2017-03-14 01:44+0200, Michael S. Tsirkin:
> > Guests running Mac OS 5, 6, and 7 (Leopard through Lion) have a problem:
> > unless explicitly provided with kernel command line argument
> > "idlehalt=0" they'd implicitly assume MONITOR
On Thu, Mar 02, 2017 at 12:24:25PM -0300, Gabriel Krisman Bertazi wrote:
> Daniel Vetter writes:
>
> > I want to split up a few more things and document some details better
> > (like how exactly to subclass drm_atomic_state). And maybe also split
> > up the helpers a bit per-topic, but this shoul
On Mon, Mar 13, 2017 at 04:41:08PM -0600, Jonathan Corbet wrote:
> On Mon, 13 Mar 2017 19:16:54 +0100
> Daniel Vetter wrote:
>
> > > Awesome! Can you pls send me/dri-devel a pull request with a stable tag
> > > for drm-misc, so that I can apply all the drm diagram patches?
> >
> > Yes I'm anno
2017-03-14 01:44+0200, Michael S. Tsirkin:
> Guests running Mac OS 5, 6, and 7 (Leopard through Lion) have a problem:
> unless explicitly provided with kernel command line argument
> "idlehalt=0" they'd implicitly assume MONITOR and MWAIT availability,
> without checking CPUID.
>
> We currently em
On Tue, 14 Mar 2017 10:39:02 +0200
Tamara Diaconita wrote:
> - If set to a nonzero value, contains a pointer to a NUL-terminated
> + If set to a nonzero value, contains a pointer to a NULL-terminated
This one is actually correct as-is. NUL is an ASCII character zero, as
one would find at the
On Tue, 14 Mar 2017 15:06:40 +0200
Daniel Baluta wrote:
> Also for easier reviewing next patches you can mention in the
> commit message what were the typos:
>
> e.g: witdh -> width
I'm not sure that's helpful in a change like this which is fixing up a
lot of different mistakes - I have to read
On Tue, Mar 14, 2017 at 10:38 AM, Tamara Diaconita
wrote:
> Fix typos in admin-guide directory.
> Make documentation clear and grammatically correct.
>
> Signed-off-by: Tamara Diaconita
Also for easier reviewing next patches you can mention in the
commit message what were the typos:
e.g: witdh
On Tue, 14 Mar 2017, Tamara Diaconita wrote:
> Should I keep this in mind for the next patches or should I also reorganize
> this patch?
I didn't suggest any reorganization. I just meant that if you find one
file in which a certain word is misspelled, then you may find the same
problem in othe
On Tue, 14 Mar 2017, Julia Lawall wrote:
> On Tue, 14 Mar 2017, Tamara Diaconita wrote:
>
>> Fix typos in x86 directory.
>> Make documentation clear and grammatically correct.
>>
>> Signed-off-by: Tamara Diaconita
>> ---
>> Documentation/x86/boot.txt | 4 ++--
>> 1 file changed, 2 insertions(+),
Emulate the HYPCALL instruction added in the VZ ASE and used by the MIPS
paravirtualised guest support that is already merged. The new hypcall.c
handles arguments and the return value. No actual hypercalls are yet
supported, but this still allows us to safely step over hypercalls and
set an error c
Add a new KVM_CAP_MIPS_64BIT capability to indicate that 64-bit MIPS
guests are available and supported. In this case it should still be
possible to run 32-bit guest code. If not available it won't be possible
to run 64-bit guest code and the instructions may not be available, or
the kernel may not
Add emulation of Memory Accessibility Attribute Registers (MAARs) when
necessary. We can't actually do anything with whatever the guest
provides, but it may not be possible to clear Guest.Config5.MRP so we
have to emulate at least a pair of MAARs.
Signed-off-by: James Hogan
Cc: Paolo Bonzini
Cc:
Add support for VZ guest CP0_SegCtl0, CP0_SegCtl1, and CP0_SegCtl2
registers, as found on P5600 and P6600 cores. These guest registers need
initialising, context switching, and exposing via the KVM ioctl API when
they are present.
They also require the GVA -> GPA translation code for handling a GV
Add support for VZ guest CP0_PWBase, CP0_PWField, CP0_PWSize, and
CP0_PWCtl registers for controlling the guest hardware page table walker
(HTW) present on P5600 and P6600 cores. These guest registers need
initialising on R6, context switching, and exposing via the KVM ioctl
API when they are prese
Add the main support for the MIPS Virtualization ASE (A.K.A. VZ) to MIPS
KVM. The bulk of this work is in vz.c, with various new state and
definitions elsewhere.
Enough is implemented to be able to run on a minimal VZ core. Further
patches will fill out support for guest features which are optiona
Add support for VZ guest CP0_ContextConfig and CP0_XContextConfig
(MIPS64 only) registers, as found on P5600 and P6600 cores. These guest
registers need initialising, context switching, and exposing via the KVM
ioctl API when they are present.
Signed-off-by: James Hogan
Cc: Paolo Bonzini
Cc: "Ra
Add support for VZ guest CP0_BadInstr and CP0_BadInstrP registers, as
found on most VZ capable cores. These guest registers need context
switching, and exposing via the KVM ioctl API when they are present.
Signed-off-by: James Hogan
Cc: Paolo Bonzini
Cc: "Radim Krčmář"
Cc: Ralf Baechle
Cc: Jon
Add new KVM_CAP_MIPS_VZ and KVM_CAP_MIPS_TE capabilities, and in order
to allow MIPS KVM to support VZ without confusing old users (which
expect the trap & emulate implementation), define and start checking
KVM_CREATE_VM type codes.
The codes available are:
- KVM_VM_MIPS_TE = 0
This is the c
This series is based on v4.11-rc2.
My hope is to take this series via the MIPS KVM tree for 4.12, possibly
with a topic branch containing the MIPS architecture changes (patches
1-6).
This series implements basic support for the MIPS Virtualization Module
(generally known as VZ) in KVM, which adds
On Tue, 14 Mar 2017, Tamara Diaconita wrote:
> Fix typos in admin-guide directory.
> Make documentation clear and grammatically correct.
You may want to collect the words in which you find problems, and see if
other files have the same problems.
julia
>
> Signed-off-by: Tamara Diaconita
> --
On Tue, 14 Mar 2017, Tamara Diaconita wrote:
> Fix typos in x86 directory.
> Make documentation clear and grammatically correct.
>
> Signed-off-by: Tamara Diaconita
> ---
> Documentation/x86/boot.txt | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/x86
Fix typos in x86 directory.
Make documentation clear and grammatically correct.
Signed-off-by: Tamara Diaconita
---
Documentation/x86/boot.txt | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/Documentation/x86/boot.txt b/Documentation/x86/boot.txt
index 5e9b826..694979a 10
Fix typos in admin-guide directory.
Make documentation clear and grammatically correct.
Signed-off-by: Tamara Diaconita
---
Changes since v1:
*Remove the changes in tainted-kernels.rst file.
Documentation/admin-guide/kernel-parameters.rst | 2 +-
Documentation/admin-guide/ras.rst
On 03/13/2017 12:43 PM, Jose Abreu wrote:
> Hi Neil,
>
>
> On 09-03-2017 14:27, Jose Abreu wrote:
>> Hi Neil,
>>
>>
>> On 08-03-2017 12:12, Neil Armstrong wrote:
>>> Hi Jose,
>>>
>>> It seems here that we only have the RGB444<->YUV444 8bit tables, from the
>>> Amlogic
>>> source I have the follo
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