Re: [PATCHv8 1/4] EDAC, altera: Add Altera L2 Cache and OCRAM EDAC Support

2016-01-21 Thread Vladimir Zapolskiy
Hi Thor, On 21.01.2016 19:34, ttha...@opensource.altera.com wrote: > From: Thor Thayer > > Adding L2 Cache and On-Chip RAM EDAC support for the > Altera SoCs using the EDAC device model. The SDRAM > controller is using the Memory Controller model. > > Each type of ECC is individually configura

[RFC PATCH] codingstyle: improve elisp for a better experience

2016-01-21 Thread Geyslan G. Bem
This patch does use of more emacs functionalities which deliver to the user indentation, commenting and white space highlighting. As known tabs are the higher law and the prior elisp code enforces that law for any lineup indentation. However some trees have specific rules about line continuation

Re: [PATCH v15 0/6] altera fpga area and fpga bus

2016-01-21 Thread Moritz Fischer
Hi Alan, On Thu, Jan 21, 2016 at 5:42 PM, atull wrote: > If you want to send me a Xilinx example of usage for me to include in that > document, that would be useful also. I think you might have sent me > something a while ago, but I can't find it now. Will do. I'll clean up some of my examples

Re: [PATCH v15 1/6] fpga: add bindings document for fpga area and fpga bus

2016-01-21 Thread Moritz Fischer
Hi Alan, On Thu, Jan 21, 2016 at 6:21 PM, atull wrote: > target-path = "/amba/fpga_bus@0/devcfg@f8007000"; derp ... building in the driver helps ... all good on your side ;-) Cheers, Moritz -- To unsubscribe from this list: send the line "unsubscribe linux-doc" in the body of a mess

[PATCHv8 3/4] ARM: socfpga: enable L2 cache ECC on startup

2016-01-21 Thread tthayer
From: Dinh Nguyen This patch enables the ECC for L2 cache on machine startup. The ECC has to be enabled before data is stored in memory otherwise the ECC will fail on reads. Signed-off-by: Thor Thayer Signed-off-by: Dinh Nguyen --- v8: Address community suggestions for strings. Fix string base

[PATCHv8 2/4] ARM: dts: Add Altera L2 Cache and OCRAM EDAC entries

2016-01-21 Thread tthayer
From: Thor Thayer Adding the device tree entries and bindings needed to support the Altera L2 cache and On-Chip RAM EDAC. This patch relies upon an earlier patch to declare and setup On-chip RAM properly. http://www.spinics.net/lists/devicetree/msg51117.html Signed-off-by: Thor Thayer Signed-of

[PATCHv8 4/4] ARM: socfpga: Enable OCRAM ECC on startup

2016-01-21 Thread tthayer
From: Dinh Nguyen This patch enables the ECC for On-Chip RAM on machine startup. The ECC has to be enabled before data is stored in memory otherwise the ECC will fail on reads. Signed-off-by: Thor Thayer Signed-off-by: Dinh Nguyen --- v8: Address community comments on strings. Fix match string

[PATCHv8 1/4] EDAC, altera: Add Altera L2 Cache and OCRAM EDAC Support

2016-01-21 Thread tthayer
From: Thor Thayer Adding L2 Cache and On-Chip RAM EDAC support for the Altera SoCs using the EDAC device model. The SDRAM controller is using the Memory Controller model. Each type of ECC is individually configurable. Signed-off-by: Thor Thayer Signed-off-by: Dinh Nguyen --- v8: Remove MASK

Re: [PATCH v15 5/6] fpga: fpga-area and fpga-bus: device tree control for FPGA

2016-01-21 Thread atull
On Thu, 21 Jan 2016, Moritz Fischer wrote: > Hi Alan, > > minor nits inline: > > On Wed, Jan 20, 2016 at 8:24 PM, wrote: > > > v15: Add altr,fpga-bus implementation > > Change compatible string "fpga-area" -> "altr,fpga-area" > > Doesn't look that way down there. Or am I reading the cod

Re: [PATCH v15 1/6] fpga: add bindings document for fpga area and fpga bus

2016-01-21 Thread atull
On Thu, 21 Jan 2016, Moritz Fischer wrote: > Hi Alan, > > I tried getting a simple example to work with overlays, however so far > I failed getting > the child nodes to probe drivers, maybe you have an idea? The fpga > image is loaded just fine. > > in dts: > >fpga_bus@0 { >

[PATCH] ACPI / tables: Add acpi_force_32bit_fadt_addr option to force 32 bit FADT addresses

2016-01-21 Thread Colin King
From: Colin Ian King BugLink: https://bugs.launchpad.net/bugs/1529381 Some HP laptops seem to have invalid 64 bit FADT X_PM* addresses which are causing various boot issues. In these cases, it would be useful to force ACPI to use the valid legacy 32 bit equivalent PM addresses. Add a acpi_forc

Re: [PATCH v15 0/6] altera fpga area and fpga bus

2016-01-21 Thread atull
On Thu, 21 Jan 2016, Moritz Fischer wrote: > Hi Alan, > > On Wed, Jan 20, 2016 at 8:24 PM, wrote: > > From: Alan Tull > > > > For v15, I'm not using the FPGA Manager as the bus. I'm adding a FPGA Bus; > > the FPGA Manager and bridges go below it. > > > > I've gotten enough feedback that my pr

Re: [PATCH v15 2/6] add sysfs document for fpga bridge class

2016-01-21 Thread atull
On Wed, 20 Jan 2016, at...@opensource.altera.com wrote: > From: Alan Tull > > Add documentation for new FPGA bridge class's sysfs interface. > > Signed-off-by: Alan Tull I've received two emails that there was no patch in this email. The copy I received has 11 lines of changes, adding one fi

[PATCH 10/16] perf tools: Document the perf sysctls

2016-01-21 Thread Arnaldo Carvalho de Melo
From: Ben Hutchings perf_event_paranoid was only documented in source code and a perf error message. Copy the documentation from the error message to Documentation/sysctl/kernel.txt. perf_cpu_time_max_percent was already documented but missing from the list at the top, so add it there. Signed-

Re: [PATCH v15 1/6] fpga: add bindings document for fpga area and fpga bus

2016-01-21 Thread Moritz Fischer
Hi Alan, I tried getting a simple example to work with overlays, however so far I failed getting the child nodes to probe drivers, maybe you have an idea? The fpga image is loaded just fine. in dts: fpga_bus@0 { compatible = "altr,fpga-bus", "simple-bus";

Re: [PATCH v15 5/6] fpga: fpga-area and fpga-bus: device tree control for FPGA

2016-01-21 Thread Moritz Fischer
Hi Alan, minor nits inline: On Wed, Jan 20, 2016 at 8:24 PM, wrote: > v15: Add altr,fpga-bus implementation > Change compatible string "fpga-area" -> "altr,fpga-area" Doesn't look that way down there. Or am I reading the code wrong? > +static const struct of_device_id fpga_area_of_match

Re: [PATCH RESEND] perf: Document the perf sysctls

2016-01-21 Thread Arnaldo Carvalho de Melo
Em Tue, Jan 19, 2016 at 09:35:15PM +, Ben Hutchings escreveu: > perf_event_paranoid was only documented in source code and a perf > error message. Move the documentation from the error message to > Documentation/sysctl/kernel.txt. > > perf_cpu_time_max_percent was already documented but missi

Re: [PATCH v15 2/6] add sysfs document for fpga bridge class

2016-01-21 Thread Moritz Fischer
On Thu, Jan 21, 2016 at 1:17 PM, Måns Rullgård wrote: > I don't see a patch in this email. So it's not just me :-) Cheers, Moritz -- To unsubscribe from this list: send the line "unsubscribe linux-doc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.ke

Re: [PATCH v15 2/6] add sysfs document for fpga bridge class

2016-01-21 Thread Måns Rullgård
writes: > From: Alan Tull > > Add documentation for new FPGA bridge class's sysfs interface. > > Signed-off-by: Alan Tull I don't see a patch in this email. -- Måns Rullgård -- To unsubscribe from this list: send the line "unsubscribe linux-doc" in the body of a message to majord...@vger.ker

Re: [PATCH v15 0/6] altera fpga area and fpga bus

2016-01-21 Thread Moritz Fischer
Hi Alan, On Wed, Jan 20, 2016 at 8:24 PM, wrote: > From: Alan Tull > > For v15, I'm not using the FPGA Manager as the bus. I'm adding a FPGA Bus; > the FPGA Manager and bridges go below it. > > I've gotten enough feedback that my proposals are Altera specific that I am > going with that and ch