?
flush_cache_louis does not disable the d cache. This is not the
recommended sequence
for core power down.
Thanks
Sandeep Tripathy
Broadcom
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Hi Daniel,
- L1 D$ clean ( SCTLR C bit clear, DCCISW, clear SMP) is part of
the recommended sequence for Individual core power down .
- If a core is powered down having dirty lines in L1 then the
system should encounter an issue (abort) very easily. May be the first
me
if the understanding is wrong.
Thanks
Sandeep
On 9 April 2014 13:24, Daniel Lezcano wrote:
>
> Hi Sandeep,
>
>
>
> On 04/09/2014 07:15 AM, Sandeep Tripathy wrote:
>
>> Hi Daniel,
>> - L1 D$ clean ( SCTLR C bit clear, DCCISW, clear S
Hi Meraj,
We only want to count the wakeup sources (eg: irq/ipi etc *). Hence
the total count for an irq /ipi can differ.
* Note there can be spurious wakeups in some systems. ie: core exiting idle
without an irq.
Thanks
Sandeep
On 20 June 2014 13:58, Mohammad Merajul Islam Molla
wrote:
le (not
> just grep irq=40/irq=18 as I mentioned before, sorry for the
> confusion) and that count does not match with the output by idlestat.
>
> Should not they match?
>
> --
> Thanks,
> -Meraj
>
> On Fri, Jun 20, 2014 at 2:42 PM, Sandeep Tripathy
> wrote:
> >
