On Thu, May 30, 2013 at 12:21:07PM -0400, Nicolas Pitre wrote:
> On Thu, 30 May 2013, Dave Martin wrote:
>
> > So, the problem is the hacked DT bindings we're using for vexpress,
> > which aren't compatible with upstream -- the perf changes assume
> > these non-standard bindings are in use.
> >
>
On Thu, 30 May 2013, Dave Martin wrote:
> So, the problem is the hacked DT bindings we're using for vexpress,
> which aren't compatible with upstream -- the perf changes assume
> these non-standard bindings are in use.
>
> Your fix won't work for platforms which describe multiple CPU PMUs in
> th
On Thu, May 30, 2013 at 06:58:53PM +0800, Andy Green wrote:
> On 30/05/13 18:50, the mail apparently from Dave Martin included:
> >On Thu, May 30, 2013 at 10:06:20AM +0800, Andy Green wrote:
> >>Hi -
> >>
> >>We're using one kernel binary with BL Switcher enabled in config,
> >>but able to work on
On 30/05/13 18:50, the mail apparently from Dave Martin included:
On Thu, May 30, 2013 at 10:06:20AM +0800, Andy Green wrote:
Hi -
We're using one kernel binary with BL Switcher enabled in config,
but able to work on SoC without Big Little.
This is OK except where the BL patches touch the PMU
On Thu, May 30, 2013 at 10:06:20AM +0800, Andy Green wrote:
> Hi -
>
> We're using one kernel binary with BL Switcher enabled in config,
> but able to work on SoC without Big Little.
>
> This is OK except where the BL patches touch the PMU driver. It
> makes an assumption about BL configured ==
On Thu, May 30, 2013 at 7:36 AM, Andy Green wrote:
> Hi -
>
> We're using one kernel binary with BL Switcher enabled in config, but able
> to work on SoC without Big Little.
>
> This is OK except where the BL patches touch the PMU driver. It makes an
> assumption about BL configured == in use whi
