> Ah I think there is a misunderstanding here, damn these TLA:s.
>
> STM in U8500 == ST-Ericsson System Trace Module
> STM in coresight == ARM System Trace Macrocell
Right... I've just nearly died laughing... ;-)
We could have discussed technical details for a looong time then :-)
Thanks for be
On Tue, Feb 8, 2011 at 11:20 AM, Pawel Moll wrote:
> And as far as I know STM can be configured to do the same, but you
> should really talk to Ian - he's the resident expert in this subject :-)
> I'll forward him your questions.
Ah I think there is a misunderstanding here, damn these TLA:s.
ST
Thanks Pawel, now I understand better the Coresight architecture,
but STM has its own hardware architecture independent to Coresight not
connected to Debug Bus nor Funnel Trace bus.
STM exposes a set of registers to our main CPU for its control, it is
connected to our ST-BUS through interconnect.
I
Morning,
> y, STM is not in the same family that xTM which trace execution & data
> flow of an ARM core (non intrusive).
> STM is more at applicative trace level like printf (output console
> only).
Well, what I mean is that xTMs - ETM/PTM tracing execution flow, ITM
behaving like mentioned prin
On 7 February 2011 13:16, Pawel Moll wrote:
> > This module external interface is a pad on the chip
> > which complies to the MIPI System Trace Protocol v1.0,
> > and the actual trace output can be read by an
> > electronic probe, not by software so it cannot be intercepted by
> > the C
> This module external interface is a pad on the chip
> which complies to the MIPI System Trace Protocol v1.0,
> and the actual trace output can be read by an
> electronic probe, not by software so it cannot be intercepted by
> the CPU and reach Linux userspace.
I'm not an expert here, b
