> From: Peter Maydell [mailto:peter.mayd...@linaro.org]
> Sent: Sunday, December 12, 2010 3:02 PM
> In case you're collecting things to clean up for the next issue,
> here's
> another :-) The Rev M OMAP35x TRM says on page 1139:
>
> "In both prefetch and write-posting modes, the engine respective
On 10 December 2010 19:25, Woodruff, Richard wrote:
> The underlying functional spec which TRM started from gives this description:
>
> "In MPU filling mode, the FIFO status can be monitored through the
> FIFOPointer or through the FIFOThresholdStatus bits in the
> GPMC_PREFETCH_STATUS register.
The underlying functional spec which TRM started from gives this description:
"In MPU filling mode, the FIFO status can be monitored through the FIFOPointer
or through the FIFOThresholdStatus bits in the GPMC_PREFETCH_STATUS register.
FIFOPointer indicates the current number of available free b
