the
> notes, let me know.
>
> Best regards,
> Arvind
>
> >-Original Message-
> >From: Philippe Langlais [mailto:philippe.langl...@linaro.org]
> >Sent: Thursday, May 26, 2011 8:50 PM
> >To: Deao, Douglas; Linus Walleij; Lee Jones
> >Cc: Arv
On 27 May 2011 10:45, Arnd Bergmann wrote:
> On Thursday 26 May 2011, Philippe Langlais wrote:
> >
> > I initiate the work to build a hardware trace framework in the kernel,
> I'm
> > not started the study to
> > have a common userspace API for STM, thanks to t
Thanks Pawel, now I understand better the Coresight architecture,
but STM has its own hardware architecture independent to Coresight not
connected to Debug Bus nor Funnel Trace bus.
STM exposes a set of registers to our main CPU for its control, it is
connected to our ST-BUS through interconnect.
I
On 7 February 2011 13:16, Pawel Moll wrote:
> > This module external interface is a pad on the chip
> > which complies to the MIPI System Trace Protocol v1.0,
> > and the actual trace output can be read by an
> > electronic probe, not by software so it cannot be intercepted by
> > the C
Hi All,
This proposal is a call for contribution for a STM driver
and its possible usages in kernel tracing infrastructure.
I'd like to know if another ARM SoC plan to use or already use STM or
some similar hardware enabling the same kind of MIPI trace points.
If yes, we can share our works.
What
