On Fri, Dec 06, 2013 at 12:39:56PM +, sandeep tripathy wrote:
> Is there any rational why flush_cache_louis is necessary in cpu_suspend()
> funciton ?
Legacy.
> After saving the context it does DCCIMVA ie writes to POC the affected lines.
> So why we should clean the entire L1 here ?
Leg
On Thu, Mar 07, 2013 at 11:59:25AM +, Leo Yan wrote:
> Very appreciate the detailed answers. i'd like to discuss further more
> for the questions, so pls see below comments.
>
> On 03/07/2013 03:15 PM, Lorenzo Pieralisi wrote:
> >>
> >> 1.
[CC'ing Will]
On Mon, Mar 04, 2013 at 06:41:42AM +, Leo Yan wrote:
>
> > On Thu, Feb 14, 2013 at 05:07:43PM +, Jon Medhurst (Tixy) wrote:
> >> The function v7_coherent_kern_range uses the macro icache_line_size to
> >> read the current CPUs icache line size for the purpose of
On Fri, Feb 15, 2013 at 02:37:49PM +, Dietmar Eggemann wrote:
> dropped linux-arm-ker...@lists.infradead.org
>
>
> On 15/02/13 12:06, Jon Medhurst (Tixy) wrote:
> > On Fri, 2013-02-15 at 10:33 +, Lorenzo Pieralisi wrote:
> >> On Fri, Feb 15, 2013 at 10:04:37A
[dropped ALKML, added Pawel]
On Fri, Feb 15, 2013 at 12:06:25PM +, Jon Medhurst (Tixy) wrote:
> On Fri, 2013-02-15 at 10:33 +0000, Lorenzo Pieralisi wrote:
> > On Fri, Feb 15, 2013 at 10:04:37AM +, Jon Medhurst (Tixy) wrote:
> > > On Thu, 2013-02-14 at 17:16 +,
On Tue, Jan 15, 2013 at 06:17:37PM +, Mark Hambleton wrote:
> Hi Lorenzo,
>
> > > +obj-$(CONFIG_BIG_LITTLE) += arm_big_little.o
> > There is nothing big.LITTLE specific in all of this, so arm_idle.c would
> >be better.
>
> I figured that because the current version calls into the big.little
) += coupled.o
> > -
> > +obj-$(CONFIG_BIG_LITTLE) += arm_big_little.o
There is nothing big.LITTLE specific in all of this, so arm_idle.c would
be better.
> > obj-$(CONFIG_CPU_IDLE_CALXEDA) += cpuidle-calxeda.o
> > diff --git a/drivers/cpuidle/arm_big_little.c
>
FIG_CPU_IDLE_MULTIPLE_DRIVERS.
>
> Tested on Core2 Duo T9500 with acpi_idle [and intel_idle]
> Tested on ARM Dual Cortex-A9 U8500 (aka Snowball)
>
> V1 tested on Tegra3 and Vexpress TC2
V3 tested on TC2, hence, on the whole series
Tested-by: Lorenzo Pieralisi
>
> [1] http://w
On Fri, Oct 19, 2012 at 11:10:49AM +0100, Daniel Lezcano wrote:
[...]
> @@ -394,9 +404,9 @@ EXPORT_SYMBOL_GPL(cpuidle_disable_device);
> static int __cpuidle_register_device(struct cpuidle_device *dev)
> {
> int ret;
> - struct cpuidle_driver *cpuidle_driver = cpuidle_get_driver()
RS
enabled in the config options.
Hence, FWIW, on the entire series:
Tested-by: Lorenzo Pieralisi
>
> [1] http://www.spinics.net/lists/linux-acpi/msg37921.html
>
> Changelog:
>
> V2:
> * fixed sysfs output : /sys/devices/system/cpu/cpu[0-9]/driver/name
> * fix
On Mon, Sep 17, 2012 at 10:35:00PM +0100, Daniel Lezcano wrote:
> On 09/17/2012 10:50 PM, Rafael J. Wysocki wrote:
> > On Monday, September 17, 2012, Daniel Lezcano wrote:
> >> On 09/08/2012 12:17 AM, Rafael J. Wysocki wrote:
> >>> On Friday, September 07, 2012, Daniel Lezcano wrote:
[...]
> >>>
Hi Daniel,
thanks for this patchset.
On Wed, Jul 25, 2012 at 11:46:02AM +0100, Daniel Lezcano wrote:
> The tegra3 and big.LITTLE architecture have different cpu latencies.
> This API allows to specify a different cpu latency for a specific cpu.
>
> With the previous patches, we use the per cpuid
On Wed, Jul 11, 2012 at 05:17:44PM +0100, Jon Medhurst (Tixy) wrote:
> On Wed, 2012-07-11 at 17:00 +0100, Viresh Kumar wrote:
> > On 11 July 2012 14:32, Jon Medhurst (Tixy) wrote:
> > On Wed, 2012-07-11 at 10:57 +0100, Viresh Kumar wrote:
> > There's going to be an 'interesting' me
On Fri, Aug 19, 2011 at 03:33:45PM +0100, Amit Kucheria wrote:
> This patch is redundant with Lorenzo's new series[1]. Adding him to cc. I
> suggest you rebase on top of his latest series.
>
Yes, thanks for pointing that out.
> On 11 Aug 19, Amit Daniel Kachhap wrote:
> > These changes are neces
On Thu, Jul 28, 2011 at 05:22:38PM +0100, Amit Kachhap wrote:
> On 7 July 2011 21:20, Lorenzo Pieralisi wrote:
> >
> > This patch provides the code infrastructure needed to maintain
> > a generic per-cpu architecture implementation of idle code.
> >
> > sr_platf
On Tue, Jul 26, 2011 at 01:14:26PM +0100, Amit Kachhap wrote:
> On 7 July 2011 21:20, Lorenzo Pieralisi wrote:
> > This patch adds the required Kconfig and Makefile entries to
> > enable and compile common idle code for ARM kernel.
> >
> > Common idle code depends on C
On Thu, Jul 21, 2011 at 09:32:12AM +0100, Santosh Shilimkar wrote:
> Lorenzo, Colin,
>
> On 7/7/2011 9:20 PM, Lorenzo Pieralisi wrote:
> > From: Colin Cross
> >
> > When the cpu is powered down in a low power mode, the gic cpu
> > interface may be reset, an
Thank you very much Russell for this recap.
On Mon, Jul 11, 2011 at 07:40:10PM +0100, Russell King - ARM Linux wrote:
> On Mon, Jul 11, 2011 at 03:00:47PM +0100, Lorenzo Pieralisi wrote:
> > Well, short answer is no. On SMP we do need to save CPU registers
> > but if just on
On Mon, Jul 11, 2011 at 05:57:29PM +0100, Frank Hofmann wrote:
> On Mon, 11 Jul 2011, Lorenzo Pieralisi wrote:
>
> [ ... ]
> >>> The array of pointers is there to save pgdir on idle entry, one per-cpu.
> >>
> >> If you're going through cpu_{do_}suspe
On Mon, Jul 11, 2011 at 03:31:30PM +0100, Frank Hofmann wrote:
>
>
> On Mon, 11 Jul 2011, Lorenzo Pieralisi wrote:
>
> > On Fri, Jul 08, 2011 at 05:12:22PM +0100, Frank Hofmann wrote:
> >> Hi Lorenzo,
> >>
> >> only a few comments at this stage.
On Sat, Jul 09, 2011 at 09:45:08AM +0100, Russell King - ARM Linux wrote:
> On Sat, Jul 09, 2011 at 09:38:15AM +0100, Russell King - ARM Linux wrote:
> > On Thu, Jul 07, 2011 at 04:50:18PM +0100, Lorenzo Pieralisi wrote:
> > > +static int late_init(void)
> > > +{
>
On Fri, Jul 08, 2011 at 05:12:22PM +0100, Frank Hofmann wrote:
> Hi Lorenzo,
>
> only a few comments at this stage.
>
> The sr_entry.S code is both exclusively .arm (using conditionals and
> long-distance adr, i.e. not Thumb2-clean), and it uses post-armv5
> instructions (like wfi). Same for the
ould ask to review your patches before you send them
> out on the mailing list.
Thanks for looking at it anyway.
My apologies Russell, point taken, and it is all my fault. Consider all
the comments on the patch splitting below as taken into account from now
onwards.
>
> On Thu, Jul 07, 20
On Fri, Jul 08, 2011 at 03:29:10AM +0100, Santosh Shilimkar wrote:
> On 7/7/2011 8:50 AM, Lorenzo Pieralisi wrote:
> > This patch adds the required Kconfig and Makefile entries to
> > enable and compile common idle code for ARM kernel.
> >
> > Common idle code depends o
On Fri, Jul 08, 2011 at 03:19:51AM +0100, Santosh Shilimkar wrote:
> On 7/7/2011 8:50 AM, Lorenzo Pieralisi wrote:
> > When the system hits deep low power states the L2 cache controller
> > can lose its internal logic values and possibly its TAG/DATA RAM content.
> >
>
On Fri, Jul 08, 2011 at 03:24:38AM +0100, Santosh Shilimkar wrote:
> On 7/7/2011 8:50 AM, Lorenzo Pieralisi wrote:
> > This patch adds the code required to allocate and populate page tables
> > that are needed by save/restore code to deal with MMU off/on
> > transactions.
&
On Fri, Jul 08, 2011 at 02:58:19AM +0100, Santosh Shilimkar wrote:
> On 7/7/2011 8:50 AM, Lorenzo Pieralisi wrote:
> > This patch provides the code infrastructure needed to maintain
> > a generic per-cpu architecture implementation of idle code.
> >
> > sr_platform
On Fri, Jul 08, 2011 at 03:14:02AM +0100, Santosh Shilimkar wrote:
> On 7/7/2011 8:50 AM, Lorenzo Pieralisi wrote:
> > When a CLUSTER is powered down the SCU must be reinitialized on
> > warm-boot.
> > This patch adds a hook to reset the SCU, which implies invalidating
>
On Thu, Jul 07, 2011 at 10:20:47PM +0100, Colin Cross wrote:
> adding Rafael, since he was interested in cpu_pm notifiers.
>
> On Thu, Jul 7, 2011 at 8:50 AM, Lorenzo Pieralisi
> wrote:
> > This patch adds notifiers to manage low-power entry/exit in a platform
> > inde
Hi Santosh,
Thanks for looking at this series.
On Fri, Jul 08, 2011 at 02:45:43AM +0100, Santosh Shilimkar wrote:
> On 7/7/2011 8:50 AM, Lorenzo Pieralisi wrote:
> > In order to define a common idle interface for the kernel
> > to enter low power modes, this patch provides includ
Thanks Colin for looking at this.
On Thu, Jul 07, 2011 at 11:06:13PM +0100, Colin Cross wrote:
> On Thu, Jul 7, 2011 at 8:50 AM, Lorenzo Pieralisi
> wrote:
> > When the system hits deep low power states the L2 cache controller
> > can lose its internal logic values and possibl
On Thu, Jul 07, 2011 at 06:15:30PM +0100, Russell King - ARM Linux wrote:
> On Thu, Jul 07, 2011 at 04:50:13PM +0100, Lorenzo Pieralisi wrote:
> > This patchset is a first attempt at providing a consolidation of idle
> > code for the ARM processor architecture and a request for com
pointer, detected dynamically through cpu id.
Signed-off-by: Lorenzo Pieralisi
---
arch/arm/kernel/reset_v7.S | 109
1 files changed, 109 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/kernel/reset_v7.S
diff --git a/arch/arm/kernel/reset_v7.S
virtual addresses constants into the code, making it impossible to call
when MMU is off and virtual translation is still not up and running).
Signed-off-by: Lorenzo Pieralisi
---
arch/arm/kernel/sr_v7_helpers.S | 47 +++
1 files changed, 47 insertions(+), 0
single function to avoid playing with cacheable stack and
flush data to L3.
The current code saving context for retention mode is still a hack and must be
improved.
Fully tested on dual-core A9 cluster.
Signed-off-by: Lorenzo Pieralisi
---
arch/arm/include/asm/outercache.h | 22 +
arch
SCU at boot provided it is removed from the init
section and kept in memory.
Signed-off-by: Lorenzo Pieralisi
---
arch/arm/include/asm/smp_scu.h |3 ++-
arch/arm/kernel/smp_scu.c | 33 ++---
2 files changed, 32 insertions(+), 4 deletions(-)
diff --git a/arch
This patch adds the required Kconfig and Makefile entries to
enable and compile common idle code for ARM kernel.
Common idle code depends on CPU_PM platform notifiers to trigger
save/restore of kernel subsystems like PMU, VFP, GIC.
Signed-off-by: Lorenzo Pieralisi
---
arch/arm/Kconfig
"perf stat" command (perf stats
successfully checked against a normal run [power down disabled] through perf of
the same task).
Signed-off-by: Lorenzo Pieralisi
---
arch/arm/kernel/perf_event.c | 22 ++
1 files changed, 22 insertions(+), 0 deletions(-)
diff --
notifier is passed a (void *) argument, that in the context of
common idle code is meant to define cpu and cluster states in order to allow
the platform specific callback to handle power down/up actions accordingly.
Signed-off-by: Lorenzo Pieralisi
---
arch/arm/include/asm/cpu_pm.h | 15
: Lorenzo Pieralisi
---
arch/arm/kernel/sr_mapping.c | 78 ++
1 files changed, 78 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/kernel/sr_mapping.c
diff --git a/arch/arm/kernel/sr_mapping.c b/arch/arm/kernel/sr_mapping.c
new file mode 100644
s not meant to provide
a definitive solution.
Tested on dual-core A9 with processors being powered-down and up
according to CPU idle workloads.
Signed-off-by: Lorenzo Pieralisi
---
arch/arm/include/asm/lb_lock.h | 34
arch/arm/kernel/lb_lock.c |
suspend/resume code in the kernel and calls
into the respective subsystems (SCU and L2 for A9) in order to carry out
actions required to enter idle modes.
Signed-off-by: Lorenzo Pieralisi
---
arch/arm/kernel/sr_v7.c | 298 +++
1 files changed, 298
matching.
Fully tested on A9 dual core CPU. A8, A5 support compile tested.
Signed-off-by: Lorenzo Pieralisi
---
arch/arm/kernel/sr_arch.c | 74 +
1 files changed, 74 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/kernel/sr_arch.c
diff
dual-core A9 cluster.
Signed-off-by: Lorenzo Pieralisi
---
arch/arm/include/asm/sr_platform_api.h | 28
arch/arm/kernel/sr_api.c | 197 +
arch/arm/kernel/sr_entry.S | 213
3 files changed, 438
.
Preprocessor defines include size of data needed to save/restore
L2 state. This define value should be moved to the respective
subsystem (PL310) once the patchset IF to that subsystem is settled.
Signed-off-by: Lorenzo Pieralisi
---
arch/arm/kernel/sr.h | 162
From: Colin Cross
When the cpu is powered down in a low power mode, the vfp
registers may be reset.
This patch uses CPU_PM_ENTER and CPU_PM_EXIT notifiers to save
and restore the cpu's vfp registers.
Signed-off-by: Colin Cross
---
arch/arm/vfp/vfpmodule.c | 40 ++
From: Colin Cross
During some CPU power modes entered during idle, hotplug and
suspend, peripherals located in the CPU power domain, such as
the GIC and VFP, may be powered down. Add a notifier chain
that allows drivers for those peripherals to be notified
before and after they may be reset.
Si
From: Will Deacon
This patch adds simple definitions of cpu_reset for ARMv6 and ARMv7
cores, which disable the MMU via the SCTLR.
Signed-off-by: Will Deacon
---
arch/arm/mm/proc-v6.S |5 +
arch/arm/mm/proc-v7.S |7 +++
2 files changed, 12 insertions(+), 0 deletions(-)
diff --g
A9 Cluster through all system low-power states
supported by the patchset. A8, A5 support compile tested.
Colin Cross (3):
ARM: Add cpu power management notifiers
ARM: gic: Use cpu pm notifiers to save gic state
ARM: vfp: Use cpu pm notifiers to save vfp state
Lorenzo Pieralisi (13):
ARM: ke
From: Colin Cross
When the cpu is powered down in a low power mode, the gic cpu
interface may be reset, and when the cpu complex is powered
down, the gic distributor may also be reset.
This patch uses CPU_PM_ENTER and CPU_PM_EXIT notifiers to save
and restore the gic cpu interface registers, and
eld up. When common clk gets
> merged, the dt support will be modified to use it.
>
Ok Grant, good to know. I did not have time to check how the bindings
changed, but at least for vexpress I was registering and binding clocks
from DT. Here is the vexpress list of tasks updated.
Versat
I know are or may be working
> on DT support, and the platform they are working on (not exclusively
> Linaro work):
>
> Lennert Buytenhek (Core infrastructure & omap3)
> Thomas Abraham (Samsung)
> John Bonesio (nVidia Tegra)
> Shawn Guo and Jason Hui (Freescale imx51)
> Jo
Hi Nicolas,
I noticed that a merge of Grant's ARM DT patches stack into linaro-stable
is on the cards and this is good news.
I have a couple of questions on linaro-next though.
I think it is supposed to track mainline closely, and on this
I'd ask your thoughts please since it does not seem to be
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