Hi Richard,
This is looking really nice. A couple of really minor nits inline,
otherwise:
Reviewed-by: Jamie Iles
On Thu, Dec 22, 2011 at 03:09:10PM +0800, Richard Zhao wrote:
> The driver get cpu operation point table from device tree cpu0 node,
> and adjusts operating points using c
Hi Richard,
On Mon, Dec 19, 2011 at 11:21:40AM +0800, Richard Zhao wrote:
> It support single core and multi-core ARM SoCs. But currently it assume
> all cores share the same frequency and voltage.
>
> Signed-off-by: Richard Zhao
> ---
> .../devicetree/bindings/cpufreq/generic-cpufreq|7
On Mon, Dec 19, 2011 at 10:19:29PM +0800, Richard Zhao wrote:
> On Mon, Dec 19, 2011 at 10:05:12AM +0000, Jamie Iles wrote:
> > Hi Richard,
> >
> > On Mon, Dec 19, 2011 at 11:21:40AM +0800, Richard Zhao wrote:
> > > It support single core and multi-core ARM SoCs. But
Hi Richard,
A couple of questions inline, but otherwise looks nice!
Jamie
On Fri, Dec 16, 2011 at 06:30:59PM +0800, Richard Zhao wrote:
> It support single core and multi-core ARM SoCs. But it assume
> all cores share the same frequency and voltage.
>
> Signed-off-by: Richard Zhao
> ---
[...]
Hi Rob,
On Mon, Sep 26, 2011 at 01:33:08PM -0500, Rob Herring wrote:
> Mike,
>
> On 09/22/2011 05:26 PM, Mike Turquette wrote:
> > From: Jeremy Kerr
> >
> > Signed-off-by: Jeremy Kerr
> > Signed-off-by: Mark Brown
> > Signed-off-by: Jamie
On Mon, Sep 26, 2011 at 02:10:32PM -0500, Rob Herring wrote:
> On 09/26/2011 01:40 PM, Jamie Iles wrote:
> > On Mon, Sep 26, 2011 at 01:33:08PM -0500, Rob Herring wrote:
> >>> +static void clk_gate_set_bit(struct clk_hw *clk)
> >>> +{
> >>> + struct c
Hi Linus,
This is looking really great! A couple of pedantic nits inline, but
with the gpio ranges support I think this covers all of the bases that
we need from pin control, so thanks!
Jamie
On Mon, Aug 29, 2011 at 11:10:01AM +0200, Linus Walleij wrote:
[...]
> diff --git a/drivers/pinctrl/M
On Mon, Aug 22, 2011 at 02:38:16PM +0200, Linus Walleij wrote:
> On Sun, Aug 21, 2011 at 4:24 PM, Jamie Iles wrote:
>
> > for device tree, when the gpio
> > controllers are registered, the base is typically dynamically assigned. I
> > suspect that this can be solved in
Hi Linus,
On Fri, Aug 19, 2011 at 03:26:08PM +0100, Jamie Iles wrote:
> On Fri, Aug 19, 2011 at 04:04:54PM +0200, Linus Walleij wrote:
> > On Fri, Aug 19, 2011 at 12:48 PM, Jamie Iles wrote:
[...]
> > But yes, there is an assumption that each pin controller will only
> > d
Hi Linus,
On Fri, Aug 19, 2011 at 04:04:54PM +0200, Linus Walleij wrote:
> On Fri, Aug 19, 2011 at 12:48 PM, Jamie Iles wrote:
> > On Fri, Aug 19, 2011 at 11:53:50AM +0200, Linus Walleij wrote:
> >> +Interaction with the GPIO subsystem
> >> +=
Hi Linus,
This is looking really nice. I have a few comments/queries inline
though.
Jamie
On Fri, Aug 19, 2011 at 11:53:50AM +0200, Linus Walleij wrote:
> From: Linus Walleij
>
> This creates a subsystem for handling of pin control devices.
> These are devices that control different aspects
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